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公开(公告)号:US20150130049A1
公开(公告)日:2015-05-14
申请号:US14077019
申请日:2013-11-11
发明人: YING-JU CHEN , HSIEN-WEI CHEN
IPC分类号: H01L23/498 , H01L23/00
CPC分类号: H01L24/05 , H01L23/5226 , H01L23/528 , H01L24/03 , H01L24/06 , H01L24/13 , H01L2224/0345 , H01L2224/03462 , H01L2224/0401 , H01L2224/05008 , H01L2224/05088 , H01L2224/05092 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05684 , H01L2224/0613 , H01L2224/131 , H01L2224/14131 , H01L2224/16111 , H01L2224/16145 , H01L2224/81191 , H01L2224/81801 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要: A semiconductor device includes a carrier and a metallic structure including a metallic member, a pad and a via portion; wherein the metallic member is disposed inside the carrier, the pad is configured for receiving a solder bump and is disposed on a surface of the carrier, the via portion is configured for electrically connecting the metallic member and the pad, and the via portion is disposed proximal to an end of the pad. Further, a method of manufacturing a semiconductor device includes providing a carrier, removing a portion of the carrier for forming a via extending a surface of the carrier to an interior of the carrier, filling the via by a conductive material, and disposing the conductive material on the surface of the carrier, wherein the via is disposed proximal to an end portion of the conductive material.
摘要翻译: 半导体器件包括载体和包括金属部件,焊盘和通孔部分的金属结构; 其特征在于,所述金属部件配置在所述载体的内部,所述焊盘被构造成用于容纳焊料凸块并且设置在所述载体的表面上,所述通孔部分被构造用于电连接所述金属部件和所述焊盘,并且所述通孔部分被设置 靠近垫的一端。 此外,制造半导体器件的方法包括提供载体,去除用于形成载体的表面的载体的一部分,以将载体的表面延伸到载体的内部,用导电材料填充该通孔,并且将导电材料 在载体的表面上,其中通孔设置在导电材料的端部附近。
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公开(公告)号:US20130181347A1
公开(公告)日:2013-07-18
申请号:US13786045
申请日:2013-03-05
发明人: Hao-Yi Tsai , Hsien-Wei Chen , Yu-Wen Liu , Ying-Ju Chen , Hsiu-Ping Wei
IPC分类号: H01L23/48 , H01L21/768
CPC分类号: H01L24/05 , H01L21/768 , H01L21/76877 , H01L23/48 , H01L23/481 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05012 , H01L2224/0509 , H01L2224/05092 , H01L2224/05094 , H01L2224/05095 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/05599 , H01L2224/131 , H01L2924/00013 , H01L2924/00014 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012
摘要: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
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13.
公开(公告)号:US20120119371A1
公开(公告)日:2012-05-17
申请号:US13273031
申请日:2011-10-13
IPC分类号: H01L23/485 , H01L21/768
CPC分类号: H01L24/05 , H01L22/32 , H01L24/03 , H01L2224/02166 , H01L2224/0362 , H01L2224/0392 , H01L2224/05092 , H01L2224/05557 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033
摘要: There is provided a method of fabricating a semiconductor device including: forming an insulating film on a semiconductor substrate; forming a pad electrode on the insulating film; forming a protective film on the pad electrode; forming, on the protective film, a resist equipped with an open portion in a first region corresponding to part of the pad electrode; by using the resist as a mask, etching the protective film and etching the first region of part of the pad electrode to a predetermined depth; etching the protective film on a second region that surrounds the first region of the pad electrode; and removing the resist.
摘要翻译: 提供一种制造半导体器件的方法,包括:在半导体衬底上形成绝缘膜; 在所述绝缘膜上形成焊盘电极; 在焊盘电极上形成保护膜; 在保护膜上形成在与焊盘电极的一部分对应的第一区域中配备有开口部分的抗蚀剂; 通过使用抗蚀剂作为掩模,蚀刻保护膜并将焊盘电极的一部分的第一区域蚀刻到预定深度; 在围绕所述焊盘电极的所述第一区域的第二区域上蚀刻所述保护膜; 并除去抗蚀剂。
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公开(公告)号:US20180090458A1
公开(公告)日:2018-03-29
申请号:US15402383
申请日:2017-01-10
发明人: Han KIM , Kyung Moon JUNG , Seok Hwan KIM , Kyung Ho LEE , Kang Heon HUR
IPC分类号: H01L23/00
CPC分类号: H01L24/04 , H01L24/02 , H01L24/05 , H01L24/19 , H01L2224/02331 , H01L2224/0235 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/05008 , H01L2224/05091 , H01L2224/05092 , H01L2224/13024 , H01L2224/16225 , H01L2224/18 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/18162 , H01L2924/3512 , H01L2924/35121 , H01L2924/00
摘要: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.
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15.
公开(公告)号:US09646941B2
公开(公告)日:2017-05-09
申请号:US14077019
申请日:2013-11-11
发明人: Ying-Ju Chen , Hsien-Wei Chen
IPC分类号: H01L23/49 , H01L23/00 , H01L23/522 , H01L23/528
CPC分类号: H01L24/05 , H01L23/5226 , H01L23/528 , H01L24/03 , H01L24/06 , H01L24/13 , H01L2224/0345 , H01L2224/03462 , H01L2224/0401 , H01L2224/05008 , H01L2224/05088 , H01L2224/05092 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05684 , H01L2224/0613 , H01L2224/131 , H01L2224/14131 , H01L2224/16111 , H01L2224/16145 , H01L2224/81191 , H01L2224/81801 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要: A semiconductor device includes a carrier and a metallic structure including a metallic member, a pad and a via portion; wherein the metallic member is disposed inside the carrier, the pad is configured for receiving a solder bump and is disposed on a surface of the carrier, the via portion is configured for electrically connecting the metallic member and the pad, and the via portion is disposed proximal to an end of the pad. Further, a method of manufacturing a semiconductor device includes providing a carrier, removing a portion of the carrier for forming a via extending a surface of the carrier to an interior of the carrier, filling the via by a conductive material, and disposing the conductive material on the surface of the carrier, wherein the via is disposed proximal to an end portion of the conductive material.
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公开(公告)号:US09570384B2
公开(公告)日:2017-02-14
申请号:US14818922
申请日:2015-08-05
IPC分类号: H01L23/48 , H01L23/552 , H01L23/52 , H01L29/40 , H01L23/498 , H01L21/768 , H01L23/00
CPC分类号: H01L23/49822 , H01L21/76838 , H01L24/03 , H01L24/05 , H01L2224/0235 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/05013 , H01L2224/05024 , H01L2224/05092 , H01L2224/05553 , H01L2224/45124 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01073 , H01L2924/01079 , H01L2924/04642 , H01L2924/05042 , H01L2924/0534 , H01L2924/05432 , H01L2924/05442 , H01L2924/059 , H01L2924/05994 , H01L2924/1461 , H01L2924/01029 , H01L2924/00 , H01L2224/48
摘要: A semiconductor device can include a substrate and a trace layer positioned in proximity to the substrate and including a trace for supplying an electrical connection to the semiconductor device. Conductive layers can be positioned in proximity to the trace layer and form a bond pad. A non-conductive thin film layer can be positioned between the trace layer and the conductive layers. The thin film layer can include a via to enable the electrical connection from the trace to the bond pad. A portion of the trace between the substrate and the plurality of conductive layers can have a beveled edge.
摘要翻译: 半导体器件可以包括基板和位于基板附近的迹线层,并且包括用于向半导体器件提供电连接的迹线。 导电层可以位于跟踪层附近并形成接合焊盘。 非导电薄膜层可以位于迹线层和导电层之间。 薄膜层可以包括通孔以使得能够从迹线到接合焊盘的电连接。 衬底和多个导电层之间的迹线的一部分可以具有斜边。
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17.
公开(公告)号:US08772943B2
公开(公告)日:2014-07-08
申请号:US13313397
申请日:2011-12-07
申请人: Xueren Zhang , Kim-Yong Goh
发明人: Xueren Zhang , Kim-Yong Goh
IPC分类号: H01L29/72
CPC分类号: H01L24/05 , H01L21/563 , H01L23/49827 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05026 , H01L2224/05092 , H01L2224/05124 , H01L2224/05552 , H01L2224/05555 , H01L2224/05567 , H01L2224/05572 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05681 , H01L2224/06051 , H01L2224/061 , H01L2224/13027 , H01L2224/13147 , H01L2224/14104 , H01L2224/14131 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/73204 , H01L2924/15311 , H01L2924/3512 , H01L2924/00014 , H01L2924/00012
摘要: An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die.
摘要翻译: 集成电路管芯具有位于集成电路管芯上的所有接触焊盘上的电介质层。 在集成电路管芯的每个接触焊盘上的介电层中设置开口,以便允许在集成电路和管芯外部的电路板之间进行电耦合。 对于位于管芯的中心区域的接触焊盘,电介质层中的开口位于接触焊盘的中心区域。 对于那些位于模具周边区域的接触垫,邻近周边模具间隔开,电介质层中的开口偏离接触焊盘的中心,并且位于比芯片中心更靠近模具的中心区域 接触垫是到模具的中心区域。
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公开(公告)号:US20100283148A1
公开(公告)日:2010-11-11
申请号:US12726449
申请日:2010-03-18
申请人: Hao-Yi Tsai , Hsien-Wei Chen , Yu-Wen Liu , Ying-Ju Chen , Hsiu-Ping Wei
发明人: Hao-Yi Tsai , Hsien-Wei Chen , Yu-Wen Liu , Ying-Ju Chen , Hsiu-Ping Wei
IPC分类号: H01L23/485 , H01L21/60
CPC分类号: H01L24/05 , H01L21/768 , H01L21/76877 , H01L23/48 , H01L23/481 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05012 , H01L2224/0509 , H01L2224/05092 , H01L2224/05094 , H01L2224/05095 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/05599 , H01L2224/131 , H01L2924/00013 , H01L2924/00014 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012
摘要: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
摘要翻译: 一个实施例是一种凸块接合焊盘结构,其包括基板,该基板包括顶层,设置在顶层上的加强垫,顶层上的中间层,设置在中间层上的中间连接垫,中间层上方的外层 层和通过外层中的开口连接到中间连接焊盘的凸块下金属(UBM)。 另外的实施例可以包括将中间连接垫机械连接到加强垫的通孔。 通孔可以包括选自由固体通孔,基本上环形的通孔或五个五孔的通孔组成的组的特征。 然而,另一实施例可以包括辅助加强垫,以及将加强垫机械连接到辅助加强垫的第二通孔。
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公开(公告)号:US20180277503A1
公开(公告)日:2018-09-27
申请号:US15912858
申请日:2018-03-06
发明人: Koji Sasaki , Shingo Nagata
CPC分类号: H01L24/05 , B41J2/14072 , B41J2/1433 , B41J2/1603 , B41J2/162 , B41J2/1623 , B41J2/1629 , B41J2/1631 , B41J2/1643 , B41J2/1645 , H01L24/03 , H01L2224/03462 , H01L2224/03614 , H01L2224/0362 , H01L2224/04042 , H01L2224/05082 , H01L2224/05092 , H01L2224/05144 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2924/04941 , H01L2924/04953
摘要: A liquid ejection head substrate includes an electrode pad for receiving driving power for liquid ejection from an outside, the electrode pad including at least a conductor layer and a layer of gold. A portion of the conductor layer has an opening region, and an upper layer portion in a laminating direction above the conductor layer including the opening region has at least the layer of gold. An external connection portion connected to the outside is provided on top of the layer of gold corresponding to the opening region of the conductor layer.
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公开(公告)号:US20170271286A1
公开(公告)日:2017-09-21
申请号:US15407422
申请日:2017-01-17
发明人: YOUNGBAE KIM
IPC分类号: H01L23/00
CPC分类号: H01L24/05 , H01L2224/02125 , H01L2224/0401 , H01L2224/05086 , H01L2224/05088 , H01L2224/05092 , H01L2224/05095 , H01L2224/05097 , H01L2224/16227 , H01L2924/15311 , H01L2924/35 , H01L2924/351
摘要: A semiconductor device includes a semiconductor substrate including a circuit layer disposed therein, a bonding pad disposed on the semiconductor substrate, the bonding pad being electrically connected to the circuit layer, and a metal layer electrically connected to the bonding pad. The metal layer includes a first via electrically connected to the bonding pad, the first via providing an electrical path between the metal layer and the circuit layer, and a second via protruding toward the semiconductor substrate, the second via supporting the metal layer on the semiconductor substrate.
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