公开(公告)号：US20120097972A1

公开(公告)日：2012-04-26

申请号：US13310384

申请日：2011-12-02

申请人： Yoshiaki SUGIZAKI ,  Hideki Shibata ,  Masayuki Ishikawa ,  Hideo Tamura ,  Tetsuro Komatsu ,  Akihiro Kojima

发明人： Yoshiaki SUGIZAKI ,  Hideki Shibata ,  Masayuki Ishikawa ,  Hideo Tamura ,  Tetsuro Komatsu ,  Akihiro Kojima

IPC分类号： H01L33/50 ,  H01L33/30

CPC分类号： H01L33/62 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0753 ,  H01L33/0079 ,  H01L33/34 ,  H01L33/38 ,  H01L33/44 ,  H01L33/486 ,  H01L33/50 ,  H01L33/58 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2224/06132 ,  H01L2224/06152 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2933/0016 ,  H01L2933/0033 ,  H01L2933/0041 ,  H01L2933/0066 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for manufacturing a light emitting device includes forming a multilayer body including a light emitting layer so that a first surface thereof is adjacent to a first surface side of a translucent substrate. A dielectric film on a second surface side opposite to the first surface of the multilayer body is formed having first and second openings on a p-side electrode and an n-side electrode. A seed metal on the dielectric film and an exposed surface of the first and second openings form a p-side metal interconnect layer and an n-side metal interconnect layer separating the seed metal into a p-side seed metal and an n-side seed metal by removing a part of the seed metal. A resin is formed in a space from which the seed metal is removed.

摘要翻译： 一种制造发光器件的方法包括：形成包括发光层的多层体，使得其第一表面与透光性基板的第一表面侧相邻。 在与p层电极和n侧电极之间形成有第一和第二开口的与多层体的第一表面相对的第二表面侧上的电介质膜形成。 电介质膜上的种子金属和第一和第二开口的暴露表面形成将种子金属分离成p侧金属和n侧籽晶的p侧金属互连层和n侧金属互连层 金属，通过去除一部分种子金属。 在除去种子金属的空间中形成树脂。

公开(公告)号：US20240243083A1

公开(公告)日：2024-07-18

申请号：US18016002

申请日：2022-01-20

申请人： Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

发明人： Huatao LI ,  Zhiguang ZHANG ,  Zhongjie WANG ,  Pan ZHAO ,  Zhilliang JIANG ,  Ziyang YU ,  Shilong WANG

IPC分类号： H01L23/00 ,  G02F1/1345 ,  H10K59/90

CPC分类号： H01L24/06 ,  H01L24/05 ,  G02F1/13452 ,  H01L2224/05553 ,  H01L2224/06152 ,  H01L2924/1426 ,  H10K59/90

摘要： Provided are a driver IC and a display device. The driver IC includes at least one GOA pad area. Each of the at least one GOA pad area includes a plurality of first pads arranged in a plurality of rows and a plurality of columns. Each of the plurality of columns of the first pads is divided into at least two first pad groups arranged independently of each other. Each of the at least two of the first pad groups includes at least two of the first pads adjacent to each other, and the first pads in each of the first pad groups are electrically connected with each other. The driver IC further includes a plurality of leads electrically connected with the first pad groups, and each of the first pad groups is electrically connected with a different lead.

公开(公告)号：US20240234443A1

公开(公告)日：2024-07-11

申请号：US18618181

申请日：2024-03-27

申请人： Samsung Display Co., LTD.

发明人： Dae Geun LEE

IPC分类号： H01L27/12 ,  G02F1/1345 ,  H01L23/00 ,  H05K1/11 ,  H05K1/18 ,  H10K59/131

CPC分类号： H01L27/124 ,  G02F1/13458 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H05K1/111 ,  H01L2224/05552 ,  H01L2224/06152 ,  H01L2224/81132 ,  H01L2924/3511 ,  H05K1/189 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09427 ,  H05K2201/09709 ,  H05K2201/09954 ,  H05K2201/10128 ,  H05K2203/166 ,  H10K59/131 ,  Y02P70/50 ,  Y10T29/49005

摘要： An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.

公开(公告)号：US12009354B2

公开(公告)日：2024-06-11

申请号：US17547455

申请日：2021-12-10

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.

发明人： Ken Funaki

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/18 ,  H01L23/5386 ,  H01L24/08 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/06 ,  H01L24/94 ,  H01L2224/06152 ,  H01L2224/08145 ,  H01L2924/10156 ,  H01L2924/14511

摘要： A solid state drive (SSD) wafer device includes first and second semiconductor wafers coupled together. The first wafer may include a number of memory dies with die bond pads, and the second wafer may include a number of electrical interconnects, each including first and second terminals at opposed ends of the electrical interconnect. When the wafers are bonded together, the first terminals of the second wafer are bonded to the die bond pads of the memory dies of the first wafer. The second terminals are left exposed to couple with an SSD controller, which controls the transfer of data and signals between the memory dies of the first wafer and a host device such as a server in a datacenter.

公开(公告)号：US20240153898A1

公开(公告)日：2024-05-09

申请号：US18387656

申请日：2023-11-07

申请人： SAMSUNG ELECTRONICS CO. LTD.

发明人： Minseung JI ,  Seungduk Baek ,  Aenee Jang

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05676 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06152 ,  H01L2224/06181 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565

摘要： A semiconductor package includes a lower chip including a first lower bonding pad and a second lower bonding pad, and an upper chip disposed on the lower chip, the upper chip including a first upper bonding pad and a second upper bonding pad respectively hybrid-bonded together. The first lower and upper bonding pads have a first shape in which first and second axis lengths are the same, and are disposed in a first center region of the chips. The second lower and upper bonding pads have a second shape in which third and fourth axis lengths differ, and are disposed in a first edge region which is near a corner point of the chip. In the second lower and upper bonding pads disposed in the first edge region, the third axis length is arranged in a direction perpendicular to a radial direction from the center point.

公开(公告)号：US20230361170A1

公开(公告)日：2023-11-09

申请号：US18352632

申请日：2023-07-14

申请人： Murata Manufacturing Co., Ltd.

发明人： Fuminori MORISAWA ,  Kazuhiro UEDA

IPC分类号： H01L29/06 ,  H01L23/00 ,  H01L29/417 ,  H01L23/367

CPC分类号： H01L29/0619 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L29/41758 ,  H01L23/3675 ,  H01L2224/05553 ,  H01L2224/06152 ,  H01L2224/06519 ,  H01L2224/13014 ,  H01L2224/14152 ,  H01L2224/14519 ,  H01L2224/16235 ,  H01L2224/13024 ,  H01L2224/1411 ,  H01L2224/05548

摘要： To provide a semiconductor device and a semiconductor module that are capable of improving a heat dissipation property in the semiconductor device including a heat generating element. A semiconductor device includes: a P-type semiconductor substrate, which has a main surface and a main surface opposed to the main surface; an N-type N well, which is provided on the main surface side of the semiconductor substrate; a unit field effect transistor, which is provided in the N well; a P-type heat dissipation guard ring region, which is provided on the main surface side of the semiconductor substrate on the outside of the N well in plan view of the semiconductor substrate; wiring, which is provided on the heat dissipation guard ring region; bump placement portions; and bumps.

公开(公告)号：US20180182781A1

公开(公告)日：2018-06-28

申请号：US15901846

申请日：2018-02-21

申请人： Samsung Display Co., Ltd.

发明人： Dae Geun Lee

IPC分类号： H01L27/12 ,  H01L23/00 ,  G02F1/1345 ,  H01L27/32

CPC分类号： H01L27/124 ,  G02F1/13458 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H01L27/3276 ,  H01L2224/05552 ,  H01L2224/06152 ,  H01L2224/81132 ,  H01L2924/3511 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09427 ,  H05K2201/09709 ,  H05K2201/09954 ,  H05K2201/10128 ,  H05K2203/166 ,  Y02P70/611 ,  Y10T29/49005

摘要： An electronic device, including an array substrate, a pad portion disposed on the array substrate, and an integrated circuit disposed on the pad portion and comprising a bump portion. The pad portion includes a first sub-pad unit including a first pad having an inclined shape and a second sub-pad unit including a second pad having an inclined shape. The first pad and the second pad are symmetrically arranged with respect to an imaginary line that divides the pad portion. The pad portion is electrically connected with the bump portion.

公开(公告)号：US09941240B2

公开(公告)日：2018-04-10

申请号：US13934982

申请日：2013-07-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ming-Kai Liu ,  Chun-Lin Lu ,  Kai-Chiang Wu ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Yen-Ping Wang ,  Chia-Chun Miao

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/06152 ,  H01L2224/06179 ,  H01L2224/13005 ,  H01L2224/13028 ,  H01L2224/13116 ,  H01L2224/1403 ,  H01L2224/14152 ,  H01L2224/14179 ,  H01L2224/14515 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17104 ,  H01L2224/17515 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/0105 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/00

摘要： A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.

公开(公告)号：US20170084559A1

公开(公告)日：2017-03-23

申请号：US15230889

申请日：2016-08-08

申请人： Samsung Electronics Co., Ltd.

发明人： Myeong Soon Park ,  Hyunsoo Chung ,  Won-young Kim ,  Ae-nee Jang ,  Chanho Lee

IPC分类号： H01L23/00

CPC分类号： H01L23/50 ,  H01L24/02 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06139 ,  H01L2224/06151 ,  H01L2224/06152 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06159 ,  H01L2224/0616 ,  H01L2224/06165 ,  H01L2224/06169 ,  H01L2224/06177 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/0613

摘要： Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

公开(公告)号：US09288910B2

公开(公告)日：2016-03-15

申请号：US14555856

申请日：2014-11-28

申请人： IBIDEN CO., LTD.

发明人： Keisuke Shimizu ,  Yuichi Nakamura ,  Tsuyoshi Yamaguchi

IPC分类号： H05K1/18 ,  H05K3/30 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H05K3/46

CPC分类号： H05K1/183 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/06152 ,  H01L2224/06153 ,  H01L2224/12105 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15313 ,  H05K1/181 ,  H05K1/185 ,  H05K3/30 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/4913

摘要： A substrate with a built-in electronic component includes multiple resin insulating layers including first, second, third and fourth insulating layers, multiple conductor layers including a first wiring layer including a first pad, a second wiring layer including a second pad, and a third wiring layer including third and fourth pads, multiple via conductors including a first via connecting the first and second pads through the second insulating layer, a second via connecting the second and third pads through the third and fourth insulating layers, and a third via connected to the fourth pad through the fourth insulating layer, and an electronic component positioned a cavity through the second and third insulating layers such that the third via is connecting terminal of the component and fourth pad. The second and third vias have filled plating filling opening portions through the third and fourth insulating layers and through the fourth insulating layer.

摘要翻译： 具有内置电子部件的基板包括包括第一，第二，第三和第四绝缘层的多个树脂绝缘层，多个导体层，包括包括第一焊盘的第一布线层，包括第二焊盘的第二布线层和第三焊盘的第三布线层 包括第三和第四焊盘的布线层，多个通孔导体，包括通过第二绝缘层连接第一和第二焊盘的第一通孔，通过第三和第四绝缘层连接第二和第三焊盘的第二通孔，以及连接到 通过第四绝缘层的第四焊盘和通过第二和第三绝缘层定位空腔的电子部件，使得第三通孔是部件和第四焊盘的连接端子。 第二和第三通孔已经通过第三绝缘层和第四绝缘层填充电镀填充开口部分并穿过第四绝缘层。