公开(公告)号：US20090032822A1

公开(公告)日：2009-02-05

申请号：US11939552

申请日：2007-11-13

Applicant: Chun-Cheng Lin ,  Abram Chang ,  Sheng-Jia Sheu ,  Eddie Huang

Inventor： Chun-Cheng Lin ,  Abram Chang ,  Sheng-Jia Sheu ,  Eddie Huang

IPC: H01L33/00

CPC classification number: H05K1/0203 ,  H01L33/647 ,  H05K1/18 ,  H05K2201/10106 ,  H05K2201/10659

Abstract: A high power light emitting diode, The high power light emitting diode comprises a light emitting diode chip, a main module, two first electrode pins, two second electrode pins, and at least one heat dissipation board. The main module has a concave and the light emitting diode chip is positioned in the concave. The first electrode pins are connected to a first side of the main module and also electrically connected to the light emitting diode chip. The second electrode pins are arranged on a second side of the main module that is relative to the first electrode pins wherein the second electrode pins and the first electrode pins are electrically opposite. The second electrode pins are electrically connected to the light emitting diode chip. The heat dissipation board is connected to a part of the main module between the first electrode pin and the second electrode pin.

Abstract translation: 大功率发光二极管，大功率发光二极管包括发光二极管芯片，主模块，两个第一电极引脚，两个第二电极引脚和至少一个散热板。 主模块具有凹面，发光二极管芯片位于凹面。 第一电极引脚连接到主模块的第一侧，并且电连接到发光二极管芯片。 第二电极引脚布置在主模块的相对于第一电极引脚的第二侧，其中第二电极引脚和第一电极引脚电气相对。 第二电极引脚电连接到发光二极管芯片。 散热板与主模块的一部分连接在第一电极销和第二电极销之间。

公开(公告)号：US20080137315A1

公开(公告)日：2008-06-12

申请号：US11984005

申请日：2007-11-13

Applicant: Eiji Takaike

Inventor： Eiji Takaike

IPC: H05K7/02 ,  B23P11/00

CPC classification number: H05K7/02 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/30107 ,  H05K1/023 ,  H05K3/328 ,  H05K3/3442 ,  H05K3/4015 ,  H05K2201/0367 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10659 ,  H05K2201/10727 ,  H05K2203/049 ,  Y02P70/611 ,  Y10T29/49826 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic component device includes a wiring substrate having a wiring pattern, an electronic component mounted on the wiring pattern of the wiring substrate and provided with an electrode arranged on a side surface thereof, and a gold bump provided on the wiring pattern in side neighborhood of the electrode of the electronic component and bonded to the electrode of the electronic component and the wiring pattern, and the electrode of the electronic component is electrically connected to the wiring pattern through the gold bump, and the gold bump is formed by a wire bump method.

Abstract translation: 一种电子部件装置，具备布线图案的布线基板，安装在布线基板的配线图案上的电子部件，在其侧面配置有电极，以及设置在布线图案的侧面附近的金凸块 电子部件的电极与电子部件的电极和布线图案接合，电子部件的电极通过金凸块电连接到布线图案，金凸块通过引线凸块法形成 。

公开(公告)号：US20070279878A1

公开(公告)日：2007-12-06

申请号：US11443763

申请日：2006-05-31

Applicant: Xingjian Cai ,  Ke Wang ,  Qing-lun Chen

Inventor： Xingjian Cai ,  Ke Wang ,  Qing-lun Chen

IPC: H05K7/00

CPC classification number: H05K1/115 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/112 ,  H05K3/3415 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09709 ,  H05K2201/10189 ,  H05K2201/10659 ,  Y02P70/613

Abstract: A circuit board may include hybrid via structures configured to connect to components, such as connectors and electronic components, mounted on the circuit board. A hybrid via structure may include one or more micro-vias configured to provide an electrical connection to a signal trace in the circuit board and one or more through-vias configured to provide a ground connection to at least one reference plane in the circuit board. In one embodiment, a plurality of circuit boards including the hybrid via structures and signal traces may be connected to establish a channel supporting differential signaling and data transfer rates of at least about 5 Gb/s. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract translation: 电路板可以包括被配置为连接到安装在电路板上的诸如连接器和电子部件的组件的混合通孔结构。 混合通孔结构可以包括一个或多个微通孔，其被配置为提供与电路板中的信号迹线的电连接以及被配置为提供到电路板中的至少一个参考平面的接地连接的一个或多个通孔。 在一个实施例中，可以连接包括混合通路结构和信号迹线的多个电路板，以建立支持至少约5Gb / s的差分信令和数据传输速率的信道。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20070257375A1

公开(公告)日：2007-11-08

申请号：US11415705

申请日：2006-05-02

Applicant: James Roland ,  Ray Parkhurst ,  Ashish Alawani ,  Marshall Maple ,  Thu Nguyen

Inventor： James Roland ,  Ray Parkhurst ,  Ashish Alawani ,  Marshall Maple ,  Thu Nguyen

IPC: H01L21/00

CPC classification number: H05K3/341 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2224/8191 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19043 ,  H05K1/0209 ,  H05K2201/09781 ,  H05K2201/10659 ,  H05K2201/10969 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: An electronic package. The electronic package includes an electronic component having a heat producing device, an attachment piece, and at least two attachment units. Each unit includes an attachment pillar having a mating surface, a solder layer formed on the mating surface, and an attachment pad located on the attachment piece. The pillar of each unit is attached to its unit attachment pad via its unit solder layer and is otherwise attached to the electronic component. One pillar at least partially covers the heat producing device. Prior to attachment of pillars to their associated unit pads, the unit solder layer of the pillar at least partially covering the heat producing device is patterned to cover less than its mating surface, and the pillar at least partially covering the heat producing device is thermally connected to the heat producing device and to its unit attachment pad via its unit solder layer.

Abstract translation: 电子包装。 电子包装包括具有发热装置，附件和至少两个附接单元的电子部件。 每个单元包括具有配合表面的附接柱，形成在配合表面上的焊料层和位于附件上的附接垫。 每个单元的支柱通过其单元焊料层附接到其单元附接垫，并且否则附接到电子部件。 一支柱至少部分地覆盖发热装置。 在将支柱附接到其相关联的单元焊盘之前，至少部分覆盖发热装置的柱的单元焊料层被图案化以覆盖小于其配合表面，并且至少部分覆盖发热装置的柱被热连接 通过其单元焊料层到制热装置和其单元附接垫。

公开(公告)号：US20070002254A1

公开(公告)日：2007-01-04

申请号：US11514960

申请日：2006-09-05

Applicant: Kazuhiro Ogawa ,  Kazuhiko Yanagawa

Inventor： Kazuhiro Ogawa ,  Kazuhiko Yanagawa

IPC: G02F1/1345

CPC classification number: G02F1/13452 ,  G02F1/134363 ,  H01L2924/0002 ,  H05K1/117 ,  H05K3/244 ,  H05K3/28 ,  H05K3/323 ,  H05K3/3452 ,  H05K3/361 ,  H05K2201/09709 ,  H05K2201/10659 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A display device includes a display panel, a printed circuit board and a semiconductor device of a film carrier type which is disposed to lie between the liquid crystal display panel and the printed circuit board and is mounted on a film carrier. First terminals of the film carrier are connected by a first anisotropic conductive film to terminals of the printed circuit board and second terminals of the film carrier are connected to terminals of the display panel by a second anistropic conductive film.

公开(公告)号：US20050236706A1

公开(公告)日：2005-10-27

申请号：US10881561

申请日：2004-06-30

Applicant: Isao Ochiai ,  Masato Take

Inventor： Isao Ochiai ,  Masato Take

IPC: H01L23/50 ,  H01L21/50 ,  H01L23/06 ,  H01L23/28 ,  H01L23/34 ,  H01L23/48 ,  H01L23/495 ,  H01L25/00 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K1/0203 ,  H01L23/49568 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/3426 ,  H05K2201/10659 ,  H05K2201/10689 ,  H01L2924/00 ,  H01L2924/20754 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: The related arts have difficulty in efficiently dissipating the heat generated by a resin-molded semiconductor element, and thus have the problem of thermal stress causing damage to the semiconductor element. To solve the problem, a semiconductor device of the preferred embodiments includes common leads coupled to an island, and a part of the common leads projects out from a resin seal body. The projecting common leads have a coupling portion. When mounting the semiconductor device, the common leads are bridged with brazing material. Thus, the heat generated by an integrated circuit chip mounted on the island is dissipated through the common leads to the outside of the resin seal body. In the preferred embodiments of the invention, a further improvement in heat dissipation characteristics can be accomplished by increasing the surface areas of the common leads.

Abstract translation: 相关技术难以有效地消散由树脂模制的半导体元件产生的热量，因此具有导致半导体元件损坏的热应力的问题。 为了解决这个问题，优选实施例的半导体器件包括耦合到岛的公共引线，并且一部分公共引线从树脂密封体突出。 突出的公共引线具有联接部分。 当安装半导体器件时，公共引线用钎焊材料桥接。 因此，安装在岛上的集成电路芯片产生的热量通过公共引线消耗到树脂密封体的外部。 在本发明的优选实施例中，可以通过增加公共引线的表面积来实现散热特性的进一步改进。

公开(公告)号：US20050162604A1

公开(公告)日：2005-07-28

申请号：US11075797

申请日：2005-03-10

Applicant: Kazuhiro Ogawa ,  Kazuhiko Yanagawa

Inventor： Kazuhiro Ogawa ,  Kazuhiko Yanagawa

IPC: G02F1/1345 ,  G02F1/13 ,  G09F9/00 ,  H01L21/60 ,  H05K1/11 ,  H05K3/24 ,  H05K3/28 ,  H05K3/32 ,  H05K3/36

CPC classification number: G02F1/13452 ,  G02F1/134363 ,  H01L2924/0002 ,  H05K1/117 ,  H05K3/244 ,  H05K3/28 ,  H05K3/323 ,  H05K3/3452 ,  H05K3/361 ,  H05K2201/09709 ,  H05K2201/10659 ,  H05K2201/10681 ,  H01L2924/00

Abstract: A display device which provides reliable connection between a semiconductor device and a printed circuit board includes a display panel, a printed circuit board disposed close to the display panel, and a semiconductor device of a film carrier type which is disposed to lie between the display panel and the printed circuit board, and terminals of the semiconductor device are respectively connected by an anisotropic conductive film to terminals of the printed circuit board that are disposed in opposition to the respective terminals of the semiconductor device.

Abstract translation: 提供半导体器件和印刷电路板之间的可靠连接的显示装置包括显示面板，靠近显示面板设置的印刷电路板，以及设置在显示面板之间的薄膜载体型半导体器件 并且印刷电路板和半导体器件的端子分别通过各向异性导电膜连接到与半导体器件的各个端子相对设置的印刷电路板的端子。

公开(公告)号：US06717066B2

公开(公告)日：2004-04-06

申请号：US10004002

申请日：2001-11-30

Applicant: Gilroy J. Vandentop ,  Yuan-Liang Li

Inventor： Gilroy J. Vandentop ,  Yuan-Liang Li

IPC: H01L2348

CPC classification number: H01L24/73 ,  H01L23/49827 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10659 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49169 ,  H01L2924/00

Abstract: To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system are also described.

Abstract translation: 为了适应由封装的或未封装的裸片和衬底的不同热膨胀系数（CTE）产生的热应力，封装包含两个或多个不同的互连区域。 位于模具的中心区域中的第一互连区域采用相对较硬的互连结构。 位于模具周边附近的第二互连区采用相对顺应的互连结构。 位于第一和第二互连区之间并具有与第一和第二区之间的顺应性质量的互连结构的附加互连区可以任选地被采用。 在一个实施例中，在第一互连区域中使用提供低电阻的焊接连接，并且在第二互连区域中使用诸如纳米脉冲的顺应连接。 还描述了制造方法以及将包装应用于电子组件，电子系统和数据处理系统。

公开(公告)号：US20040052077A1

公开(公告)日：2004-03-18

申请号：US10641759

申请日：2003-08-14

Inventor： Kelvin Shih

IPC: F21V029/00

CPC classification number: H01L33/647 ,  H01L33/62 ,  H01L2224/48091 ,  H05K1/021 ,  H05K1/182 ,  H05K2201/10106 ,  H05K2201/10659 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A light emitting diode (LED)has an integrated heat sink structure for removing heat from an LED junction and for dissipating heat from the junction to the ambient air. The anode and the cathode both either act as or are coupled to a thermally conductive material which acts as the heat sink. In one embodiment, the heat sink forms a mounting configuration that allows air to circulate around multiple surfaces to maximize heat dissipation. As a result, the LED junction temperature remains low, allowing the LED to by driven with higher currents and generate a higher light output without adverse temperature-related effects.

Abstract translation: 发光二极管（LED）具有集成的散热器结构，用于从LED结点移除热量，并将热量从结到散热到环境空气。 阳极和阴极既可以作为或耦合到用作散热器的导热材料。 在一个实施例中，散热器形成允许空气围绕多个表面循环以最大化散热的安装构造。 结果，LED结温度保持较低，允许LED以更高的电流驱动，并产生更高的光输出，而不会产生不利的温度相关影响。

公开(公告)号：US20030231088A1

公开(公告)日：2003-12-18

申请号：US10372898

申请日：2003-02-26

Inventor： Hiroshi Kikuchi ,  Norio Nakazato ,  Hideko Ando ,  Takashi Suga ,  Satoru Isomura ,  Takashi Kubo ,  Hiroyasu Sasaki ,  Masanori Fukuhara ,  Naotaka Tanaka ,  Fujiaki Nose

IPC: H01L023/34

CPC classification number: H05K1/0243 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1903 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K3/361 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10659 ,  H05K2201/10681 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.