公开(公告)号：US07578056B2

公开(公告)日：2009-08-25

申请号：US11640818

申请日：2006-12-18

Applicant: Farrah J. Johnson ,  Tongbi Jiang

Inventor： Farrah J. Johnson ,  Tongbi Jiang

IPC: H05K3/34

CPC classification number: H01L21/56 ,  H01L21/283 ,  H01L21/2885 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/16225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149

Abstract: A method for encapsulating a flip chip in one step is disclosed. The flip chip is immersed in a polymer bath to apply a coating of the polymer to the surface of the flip chip except for the distal end of the conductive projections on the flip chip electrically conductive pads. The coated flip chip is exposed to ultraviolet light or heat (e.g., IR radiation) so that the coating is at least partially cured.

Abstract translation: 公开了一种在一个步骤中封装倒装芯片的方法。 将倒装芯片浸入聚合物浴中，将聚合物涂层施加到倒装芯片的表面，除了倒装芯片导电焊盘上的导电突起的远端。 涂覆的倒装芯片暴露于紫外光或热（例如，IR辐射），使得涂层至少部分固化。

公开(公告)号：US07411297B2

公开(公告)日：2008-08-12

申请号：US11407435

申请日：2006-04-20

Applicant: Shijian Luo ,  Tongbi Jiang

Inventor： Shijian Luo ,  Tongbi Jiang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/10 ,  H01L21/561 ,  H01L21/563 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a coating on the interconnect elements of the microfeature workpiece, producing a layer over the surface of the microfeature workpiece after forming the coating, and removing the coating from at least a portion of the individual interconnect elements. The coating has a surface tension less than a surface tension of the interconnect elements to reduce the extent to which the material in the layer wicks up the interconnect elements and produces a fillet at the base of the individual interconnect elements.

Abstract translation: 本文公开了微特征装置，微特征工件以及用于制造微特征装置和微特征工件的方法。 微型工件具有集成电路，表面和从表面突出并且在表面上排列成阵列的多个互连元件。 在一个实施例中，一种方法包括在微特征工件的互连元件上形成涂层，在形成涂层之后在微特征工件的表面上产生一层，以及从单个互连元件的至少一部分去除涂层。 涂层具有小于互连元件的表面张力的表面张力，以减少层中的材料吸收互连元件的程度，并在单个互连元件的基部产生圆角。

公开(公告)号：US07253025B2

公开(公告)日：2007-08-07

申请号：US10923360

申请日：2004-08-20

Applicant: Tongbi Jiang ,  J. Michael Brooks

Inventor： Tongbi Jiang ,  J. Michael Brooks

IPC: H01L21/44 ,  H01L29/40

CPC classification number: H01L24/16 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48464 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/10161 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A microelectronic device and method for manufacture. In one embodiment, two microelectronic substrates are directly bonded to each other without an intermediate adhesive material. For example, each microelectronic substrate can include a first surface, a second surface opposite the first surface, and a functional microelectronic feature coupled to a connection terminal of the microelectronic substrate. The connection terminals can be coupled to a support member, such as a leadframe or a printed circuit board, with the bond plane between the microelectronic substrates either aligned with or transverse to the support member. The microelectronic substrates can be enclosed in a protective packaging material that can include a transparent window to allow selected radiation to strike one or the other of the microelectronic substrates.

Abstract translation: 一种微电子器件及其制造方法。 在一个实施例中，两个微电子基板彼此直接接合而没有中间粘合剂材料。 例如，每个微电子衬底可以包括第一表面，与第一表面相对的第二表面，以及耦合到微电子衬底的连接端子的功能微电子特征。 连接端子可以耦合到诸如引线框架或印刷电路板的支撑构件，其中微电子衬底之间的键合平面与支撑构件对准或横向于支撑构件。 微电子衬底可以封装在保护性包装材料中，该保护性包装材料可以包括透明窗口，以允许选定的辐射冲击微电子衬底中的一个或另一个。

公开(公告)号：US20070132089A1

公开(公告)日：2007-06-14

申请号：US11301619

申请日：2005-12-13

Applicant: Tongbi Jiang ,  Zhong-Yi Xia ,  Sandhya Sandireddy

Inventor： Tongbi Jiang ,  Zhong-Yi Xia ,  Sandhya Sandireddy

IPC: H01L23/12

CPC classification number: H01L23/3128 ,  H01L23/16 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a flexed microelectronic die mounted to the support member. The flexed microelectronic die has a plurality of terminals electrically coupled to the support member and an integrated circuit operably coupled to the terminals. The die can be a processor, memory, imager, or other suitable die. The support member can be a lead frame, a plurality of electrically conductive leads, and/or an interposer substrate.

Abstract translation: 本文公开了用于制造微电子器件的微电子器件和方法。 在一个实施例中，装置包括支撑构件和安装到支撑构件的弯曲微电子模具。 柔性微电子管芯具有电耦合到支撑构件的多个端子和可操作地耦合到端子的集成电路。 模具可以是处理器，存储器，成像器或其他合适的管芯。 支撑构件可以是引线框架，多个导电引线和/或插入器基板。

公开(公告)号：US07199037B2

公开(公告)日：2007-04-03

申请号：US11413682

申请日：2006-04-27

Applicant: Shijian Luo ,  Tongbi Jiang

Inventor： Shijian Luo ,  Tongbi Jiang

IPC: H01L21/44

CPC classification number: H01L24/10 ,  H01L21/561 ,  H01L21/563 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a coating on the interconnect elements of the microfeature workpiece, producing a layer over the surface of the microfeature workpiece after forming the coating, and removing the coating from at least a portion of the individual interconnect elements. The coating has a surface tension less than a surface tension of the interconnect elements to reduce the extent to which the material in the layer wicks up the interconnect elements and produces a fillet at the base of the individual interconnect elements.

Abstract translation: 本文公开了微特征装置，微特征工件以及用于制造微特征装置和微特征工件的方法。 微型工件具有集成电路，表面和从表面突出并且在表面上排列成阵列的多个互连元件。 在一个实施例中，一种方法包括在微特征工件的互连元件上形成涂层，在形成涂层之后在微特征工件的表面上产生一层，以及从单个互连元件的至少一部分去除涂层。 涂层具有小于互连元件的表面张力的表面张力，以减少层中的材料吸收互连元件的程度，并在单个互连元件的基部产生圆角。

公开(公告)号：US07198980B2

公开(公告)日：2007-04-03

申请号：US10706576

申请日：2003-11-12

Applicant: Tongbi Jiang ,  Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

Inventor： Tongbi Jiang ,  Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

IPC: H01L23/538

CPC classification number: H01L24/97 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

Abstract translation: 多芯片半导体器件（MDSCD）封装包括大体上平面的中介层，其包括具有中心插座的基板，上表面导体以及插入件下表面上的外部连接器。 导电通孔将上表面导体与外部连接器相连。 一个或多个半导体器件可以安装在插座中，以及安装在插入件上方和/或下方并附着于其上的一个或多个其它半导体器件。 封装可以被配置为具有不显着大于最大器件的占地面积和/或不显着大于所包括的器件的组合厚度的厚度。 公开了用于组装和封装来自多芯片晶片和多中介片片或条的封装的方法。 公开了将多个封装组合成单个堆叠封装的方法。 这些方法可以包括在相同封装内使用稍微侧向延伸的中间导电元件，倒装片式电连接或两者。

公开(公告)号：US07189602B2

公开(公告)日：2007-03-13

申请号：US09998165

申请日：2001-12-03

Applicant: Tongbi Jiang ,  Zhiqiang Wu

Inventor： Tongbi Jiang ,  Zhiqiang Wu

IPC: H01L21/00

CPC classification number: H01L24/06 ,  H01L23/4827 ,  H01L23/4828 ,  H01L23/585 ,  H01L24/48 ,  H01L27/08 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2223/665 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/8546 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device is provided with a conductive layer provided on a backside of a semiconductor substrate. The conductive layer helps maintain a uniform bias voltage over the substrate. The conductive layer can also be used to apply a bias voltage to the substrate and reduce the number of bias voltage distribution regions required.

Abstract translation: 半导体器件设置有设置在半导体衬底的背面上的导电层。 导电层有助于在衬底上保持均匀的偏置电压。 导电层也可用于向衬底施加偏置电压并减少所需的偏置电压分布区域的数量。

公开(公告)号：US20060246626A1

公开(公告)日：2006-11-02

申请号：US11476467

申请日：2006-06-28

Applicant: Tongbi Jiang ,  Shijian Luo

Inventor： Tongbi Jiang ,  Shijian Luo

IPC: H01L21/50

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/14

Abstract: Methods for applying a dielectric protective layer to a wafer in wafer-level chip scale package manufacture. A flowable dielectric protective material with fluxing capability is applied over the active surface of an unbumped semiconductor wafer to cover active device areas, bond pads, test socket contact locations, and optional pre-scribed wafer street trenches. Preformed solder balls are then disposed over the bond pads, and the wafer is subjected to a heating process to reflow the solder balls and at least partially cure the dielectric protective material. During the heating process, the dielectric protective material provides a fluxing capability to enable the solder balls to wet the bond pads. In other exemplary embodiments, the dielectric protective material is applied over only intended physical contact locations and/or pre-scribed wafer street trenches, in which case the dielectric protective material need not include flux material and may additionally include a filler material.

Abstract translation: 在晶片级芯片尺寸封装制造中将晶片上施加介电保护层的方法。 具有助熔能力的可流动的介电保护材料施加在未凸起的半导体晶片的有源表面上，以覆盖有源器件区域，接合焊盘，测试插座接触位置以及可选的预刻片晶片街道沟槽。 然后将预形成的焊球设置在接合焊盘上方，并且对晶片进行加热处理以回流焊球并且至少部分地固化介电保护材料。 在加热过程中，介电保护材料提供助熔能力，以使焊球能够润湿接合焊盘。 在其它示例性实施例中，介电保护材料仅施加在预期的物理接触位置和/或预划线的晶片街道沟槽上，在这种情况下，介电保护材料不需要包括焊剂材料，并且还可以包括填充材料。

公开(公告)号：US20060194424A1

公开(公告)日：2006-08-31

申请号：US11413682

申请日：2006-04-27

Applicant: Shijian Luo ,  Tongbi Jiang

Inventor： Shijian Luo ,  Tongbi Jiang

IPC: H01L21/44

CPC classification number: H01L24/10 ,  H01L21/561 ,  H01L21/563 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a coating on the interconnect elements of the microfeature workpiece, producing a layer over the surface of the microfeature workpiece after forming the coating, and removing the coating from at least a portion of the individual interconnect elements. The coating has a surface tension less than a surface tension of the interconnect elements to reduce the extent to which the material in the layer wicks up the interconnect elements and produces a fillet at the base of the individual interconnect elements.

Abstract translation: 本文公开了微特征装置，微特征工件以及用于制造微特征装置和微特征工件的方法。 微型工件具有集成电路，表面和从表面突出并且在表面上排列成阵列的多个互连元件。 在一个实施例中，一种方法包括在微特征工件的互连元件上形成涂层，在形成涂层之后在微特征工件的表面上产生一层，以及从单个互连元件的至少一部分去除涂层。 涂层具有小于互连元件的表面张力的表面张力，以减少层中的材料吸收互连元件的程度，并在单个互连元件的基部产生圆角。

公开(公告)号：US20060172510A1

公开(公告)日：2006-08-03

申请号：US11385356

申请日：2006-03-21

Applicant: Michael Connell ,  Tongbi Jiang

Inventor： Michael Connell ,  Tongbi Jiang

IPC: H01L21/78

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/07802 ,  H01L2924/14 ,  Y10S438/976 ,  Y10T156/1082 ,  Y10T156/1092 ,  Y10T428/12535 ,  Y10T428/1443 ,  Y10T428/1457 ,  Y10T428/1471 ,  Y10T428/1495 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of microelectronic components in a batch fashion. In one embodiment, an adhesive payer is applied on a rear surface of a wafer. A plurality of spaced-apart adhesive pads are defined within the adhesive layer. Each adhesive pad may cover less than the entire back surface area of the component to which it is attached. A mounting member (e.g., dicing tape) may be attached to the adhesive layer and, in some embodiments, the adhesive layer may be treated so that the mounting member is less adherent to the adhesive pads than to other parts of the adhesive layer, easing removal of the adhesive pads with the microelectronic components.