公开(公告)号：US5891606A

公开(公告)日：1999-04-06

申请号：US727832

申请日：1996-10-07

Applicant: Vernon L. Brown

Inventor： Vernon L. Brown

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46 ,  G03F7/00

CPC classification number: H05K3/4069 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/0236 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10378 ,  H05K2203/1453 ,  H05K3/0023 ,  H05K3/184 ,  H05K3/465 ,  H05K3/4661

Abstract: A process for forming a double-sided or multi-layered circuit structure entailing the use of a fill material that forms a conductive connection between the layers of the circuit structure and photodefinable resins that form permanent dielectric layers and plateable surfaces of the circuit structure. The method includes forming a through-hole in a substrate, and then filling the through-hole with the fill material containing a metal that is catalytic to electroless copper. The fill material forms an electrical connection having oppositely-disposed connection surfaces that are coextensive with opposite surfaces of the substrate. A first photodefinable dielectric layer is then formed on each surface of the substrate, including the connection surfaces, and openings are photoimaged and developed in the dielectric layers to expose a portion of each connection surface. A second dielectric layer is then formed over each of the first dielectric layers and the exposed portions of the connection surfaces, with an opening being formed in each of the second dielectric layers to re-expose the portions of the connection surfaces and contiguous surface portions of the first dielectric layers. The exposed surface portions of the first dielectric layers and the exposed portions of the connection surfaces are then electrolessly plated with copper to form conductor traces on each side of the substrate. As a result, the traces electrically contact the connection surfaces, such that traces on opposite sides of the circuit structure are interconnected with the connection formed by the fill material in the through-hole.

Abstract translation: 一种用于形成双面或多层电路结构的方法，其需要使用形成电路结构层之间的导电连接的填充材料和形成电路结构的永久电介质层和可平板表面的可光限定树脂。 该方法包括在基底中形成通孔，然后用含有对无电铜催化的金属的填充材料填充通孔。 填充材料形成具有相对设置的连接表面的电连接，该连接表面与衬底的相对表面共同延伸。 然后在基板的每个表面上形成第一可光致电介质层，包括连接表面，并且在电介质层中对开口进行光刻和显影以暴露每个连接表面的一部分。 然后在每个第一电介质层和连接表面的暴露部分上形成第二电介质层，其中开口形成在每个第二电介质层中，以重新暴露连接表面和连续表面部分的部分 第一介电层。 然后将第一介电层的暴露表面部分和连接表面的暴露部分用铜无电镀，以在基板的每一侧上形成导体迹线。 结果，迹线电连接到连接表面，使得电路结构的相对侧上的迹线与由通孔中的填充材料形成的连接互连。

公开(公告)号：US5837427A

公开(公告)日：1998-11-17

申请号：US693655

申请日：1996-08-09

Applicant: Se Meyung Hwang ,  Keon Yang Park ,  Young Hwan Shin

Inventor： Se Meyung Hwang ,  Keon Yang Park ,  Young Hwan Shin

IPC: H05K3/46 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  G03C5/00 ,  B05D5/12

CPC classification number: H01L21/4857 ,  H05K1/115 ,  H05K3/0023 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K3/4644

Abstract: A method for manufacturing a build-up multi-layer printed circuit board is disclosed which is used in the mother board of a computer, camera-incorporated VTRs, MCMs (multi chip module), CSPs (chip size package) or portable phones. In the build-up multi-layer printed circuit board of the present invention, an inner-layer connecting state is improved. The multi-layer printed circuit board is manufactured by sequentially stacking insulating resin layers and circuit conductor layers based on a build-up method. That is, a first insulating resin layer is necessarily made to undergo an exposure and a development so as to form a first via hole 122. Then a second via hole 124 which is larger than the first via hole 122 is formed on a second insulating resin layer, thereby forming a final V shaped photo via hole 120. Thus build-up multi-layer printed circuit board is manufactured.

Abstract translation: 公开了一种用于制造积层多层印刷电路板的方法，其用于计算机的母板，配有相机的VTR，MCM（多芯片模块），CSP（芯片尺寸封装）或便携式电话。 在本发明的积层多层印刷电路板中，提高了内层连接状态。 多层印刷电路板通过基于积累方法依次堆叠绝缘树脂层和电路导体层来制造。 也就是说，必须使第一绝缘树脂层经受曝光和显影以形成第一通孔122.然后在第二绝缘树脂上形成大于第一通孔122的第二通孔124 从而形成最终的V形光通孔120.由此制造多层印刷电路板。

公开(公告)号：US5789271A

公开(公告)日：1998-08-04

申请号：US617283

申请日：1996-03-18

Applicant: Salman Akram

Inventor： Salman Akram

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/14 ,  H05K3/28 ,  H05K3/32 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46 ,  H01L21/00

CPC classification number: H05K1/113 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49827 ,  H05K3/4007 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/19107 ,  H05K1/0271 ,  H05K1/0306 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/043 ,  H05K3/143 ,  H05K3/28 ,  H05K3/325 ,  H05K3/3457 ,  H05K3/4605 ,  H05K3/4676

Abstract: A method for forming an interconnect for making a temporary or permanent electrical connection to a semiconductor dice is provided. The interconnect includes a rigid substrate on which an insulating layer and a pattern of conductors are formed. A compliant layer is formed on the insulating layer of a material such as polyimide. Vias are formed in the compliant layer with metal contacts in electrical communication with the conductors. Microbumps are formed on the compliant layer in electrical communication with the contacts and are adapted to flex with the compliant layer. The interconnect can be used to provide a temporary electrical connection for testing bare semiconductor dice. Alternately the interconnect can be used for flip chip mounting dice for fabricating multi chip modules and other electronic devices.

Abstract translation: 提供了一种用于形成用于制造与半导体裸片的暂时或永久电连接的互连的方法。 互连包括刚性基板，其上形成绝缘层和导体图案。 柔性层形成在诸如聚酰亚胺的材料的绝缘层上。 在兼容层中形成通孔，其中金属触点与导体电连通。 微胶囊形成在柔性层上，与触头电连通并且适于与柔顺层挠曲。 互连可用于提供用于测试裸半导体裸片的临时电连接。 或者，互连可以用于倒装芯片安装芯片，用于制造多芯片模块和其他电子设备。

公开(公告)号：US5664325A

公开(公告)日：1997-09-09

申请号：US410950

申请日：1995-03-27

Applicant: Naoki Fukutomi ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Kouichi Kaitou ,  Yasunobu Yoshidomi ,  Yoshihiro Takahashi

Inventor： Naoki Fukutomi ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Kouichi Kaitou ,  Yasunobu Yoshidomi ,  Yoshihiro Takahashi

IPC: H05K3/04 ,  H05K3/20 ,  H05K3/42 ,  H05K3/46 ,  H05K3/06

CPC classification number: H05K3/428 ,  H05K3/205 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K3/04 ,  H05K3/4652 ,  H05K3/4658 ,  Y10S29/016 ,  Y10T29/49156 ,  Y10T29/49158

Abstract: A wiring board is fabricated through the following steps:(A) forming, on one side of an elongated carrier metal foil made of a first metal, a thin layer with a second metal whose etching conditions are different from those of the first metal;(B) forming, on a surface of the thin layer, a desired wiring pattern with a third metal whose etching conditions are different from those of the second metal;(C) superposing the carrier metal foil on an insulating substrate with the side of the wiring pattern being positioned inside, whereby the wiring pattern is embedded in the insulating substrate; and(D) etching off the carrier metal foil and the thin layer at desired parts thereof.

Abstract translation: 通过以下步骤制造布线板：（A）在由第一金属制成的细长载体金属箔的一侧上形成具有与第一金属的蚀刻条件不同的第二金属的薄层; （B）在所述薄层的表面上形成与蚀刻条件不同于所述第二金属的第三金属的期望布线图案; （C）将所述载体金属箔叠置在所述布线图案的一侧位于绝缘基板上，由此将所述布线图案嵌入所述绝缘基板中; 和（D）在其所需部分刻蚀载体金属箔和薄层。

公开(公告)号：US5636104A

公开(公告)日：1997-06-03

申请号：US512013

申请日：1995-08-07

Applicant: Sang E. Oh

Inventor： Sang E. Oh

IPC: H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H05K3/34 ,  H05K3/46 ,  H05K7/02 ,  H01R9/09

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49827 ,  H05K3/3436 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10242 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613

Abstract: A ball grid array package includes a semiconductor chip 4, a circuit board 21 including a plurality of pattern layers of conductive wiring and dielectric layers interposed between the pattern layers which include the first pattern layer 22 and the second pattern layer 23. Electrically conductive wires are provided for interconnecting the semiconductor chip and the conductive wiring, mold resin 4 encapsulates the semiconductor chip and the wiring, and a plurality of solder balls 5 are adhered to a bottom surface of the circuit board 21 and electrically interconnected to the wires via the pattern layers. The surface mounting pad 22 is formed on the first pattern layer and a second conductive pad is formed on the second pattern layer. The first pattern layer is an outermost layer of the circuit board and the second pattern layer is just inside of the first layer so that the first and the second conductive pads form a solder ball groove mounting pad wherein a bottom surface of the mounting pad is the second conductive pad and the first conductive pad extends to the surface of the mounting pad.

Abstract translation: 球栅阵列封装包括半导体芯片4，电路板21，其包括插入在包括第一图案层22和第二图案层23的图案层之间的导电布线和电介质层的多个图案层。导电导线 提供用于互连半导体芯片和导电布线，模制树脂4封装半导体芯片和布线，并且多个焊球5粘附到电路板21的底表面并且经由图案层电连接到导线 。 表面安装焊盘22形成在第一图案层上，第二导电焊盘形成在第二图案层上。 第一图案层是电路板的最外层，第二图案层刚好在第一层的内部，使得第一和第二导电焊盘形成焊球保持垫，其中安装垫的底表面是 第二导电焊盘和第一导电焊盘延伸到安装焊盘的表面。

公开(公告)号：US5578341A

公开(公告)日：1996-11-26

申请号：US364452

申请日：1994-12-27

Applicant: Kouichi Hirosawa

Inventor： Kouichi Hirosawa

IPC: H05K3/28 ,  H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  B05D5/12

CPC classification number: H05K3/421 ,  H05K3/385 ,  H05K2201/09509 ,  H05K2203/0315 ,  H05K2203/1157 ,  H05K3/0023 ,  H05K3/4644

Abstract: A method of manufacturing a printed wiring board by a build-up technique improves the bonding force between a conductor circuit and a resin. After the surface of the first conductor pattern is roughened by oxidation, an insulating layer is formed to expose a viahole portion of the first conductor pattern. Then the resin insulating layer is roughened and the board is reduction processed before a plating operation is carried out.

Abstract translation: 通过积层技术制造印刷线路板的方法提高了导体电路和树脂之间的结合力。 在通过氧化使第一导体图案的表面粗糙化之后，形成绝缘层以露出第一导体图案的通孔部分。 然后在执行电镀操作之前，树脂绝缘层被粗糙化并且板被还原处理。

公开(公告)号：US5504992A

公开(公告)日：1996-04-09

申请号：US268866

申请日：1994-06-30

Applicant: Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Toshio Yamazaki ,  Masahiko Itabashi ,  Hirohito Ohhata

Inventor： Naoki Fukutomi ,  Yoshiaki Tsubomatsu ,  Toshio Yamazaki ,  Masahiko Itabashi ,  Hirohito Ohhata

IPC: H05K3/42 ,  H05K3/46 ,  H05K3/02

CPC classification number: H05K3/428 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K3/4652 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The object of the present invention is to provide a wiring board fabrication process which is, not only so smooth on the surface that a fine wiring pattern can be formed thereon, but also suitable for mounting electronic parts having fine pitch terminals.The present invention is a fabrication process of a wiring board which comprises a wiring conductive line embedded in the surface of an insulating substrate so that the upper face of the conductive line and the surface of the substrate are flat, and a through-hole land which is a conductive portion projected from the surface of the substrate in a through-hole portion, which is characterized in removing the conductive portion projected from the surface of the substrate in the through-hole portion so as to have a flat surface on the surface of the substrate.

Abstract translation: 本发明的目的在于提供一种线路板制造工艺，不仅在表面上光滑地形成精细的布线图案，而且还适合于安装具有细间距端子的电子部件。 本发明是一种布线板的制造工艺，其包括布置在绝缘基板的表面上的布线导线，使得导线的上表面和基板的表面平坦，以及通孔焊盘， 是在通孔部中从基板的表面突出的导电部，其特征在于，除去从通孔部中的基板的表面突出的导电部，使其在表面上具有平坦的表面 底物。

公开(公告)号：US5455393A

公开(公告)日：1995-10-03

申请号：US159234

申请日：1993-11-30

Applicant: Tutomu Ohshima ,  Hidebumi Ohnuki ,  Ryo Maniwa

Inventor： Tutomu Ohshima ,  Hidebumi Ohnuki ,  Ryo Maniwa

IPC: H05K3/34 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K1/0221 ,  H05K1/112 ,  H05K3/465 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09745 ,  H05K2203/0733 ,  H05K3/0023 ,  H05K3/3468 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayered printed wiring board includes a plurality of inner layer circuits, ground layers, first insulating layers, a second insulating layer, a surface layer circuit, and a parts mounting pad. The inner layer circuits are arranged parallel to each other in a flat manner in at least one inner layer. The ground layers are formed on and under the inner layer circuits to sandwich the inner layer circuits. The first insulating layers are respectively formed between the ground layers and the inner layer circuits to insulate the inner layer circuits from each other and the inner layer circuits from the ground layers. The second insulating layer is formed at least on an uppermost one of the ground layers and serving as a surface layer. The surface layer circuit is selectively formed on the second insulating layer. The parts mounting pad is formed at a predetermined region on the second insulating layer, has a recessed portion for fitting a lead portion of a mounting part therein, and is connected to the surface layer circuit. A method of manufacturing this printed wiring board is also disclosed.

Abstract translation: 多层印刷电路板包括多个内层电路，接地层，第一绝缘层，第二绝缘层，表面层电路和部件安装焊盘。 内层电路在至少一个内层中以平坦的方式彼此平行地布置。 接地层形成在内层电路之上和之下，以夹住内层电路。 第一绝缘层分别形成在接地层和内层电路之间，以使内层电路彼此隔离，内层电路与接地层绝缘。 第二绝缘层至少形成在最上层的一层接地层中并用作表面层。 表层电路选择性地形成在第二绝缘层上。 零件安装垫形成在第二绝缘层上的预定区域，具有用于将安装部件的引线部分嵌入其中的凹部，并连接到表面层电路。 还公开了制造该印刷线路板的方法。

公开(公告)号：US5436411A

公开(公告)日：1995-07-25

申请号：US169788

申请日：1993-12-20

Applicant: Nicholas F. Pasch

Inventor： Nicholas F. Pasch

IPC: H01L23/538 ,  H05K1/02 ,  H05K3/24 ,  H05K3/46 ,  H05K1/00

CPC classification number: H01L23/5384 ,  H05K3/4647 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H05K1/0206 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K3/243 ,  H05K3/4644

Abstract: Poor sidewall coverage of vias in substrates for multi-chip modules is alleviated by forming pillars associated with conductors on an underlying metal wiring layer. In one embodiment, the pillars are disposed underneath the conductors, causing portions of the conductors to be pushed up through an overlying insulating layer towards a metal layer overlying the insulating layer. The pillars can be electrically conductive or insulating, and can be thermally conductive. In another embodiment, the pillars are disposed atop the conductors, thereby extending at least partially through the insulating layer. These pillars are electrically conductive.

Abstract translation: 通过在下面的金属布线层上形成与导体相关联的支柱来减轻用于多芯片模块的衬底中通孔的不良侧壁覆盖。 在一个实施例中，支柱设置在导体下方，导致导体的一部分朝向覆盖绝缘层的金属层向上推过上覆绝缘层。 支柱可以是导电的或绝缘的，并且可以是导热的。 在另一个实施例中，支柱设置在导体顶部，从而至少部分延伸穿过绝缘层。 这些柱子是导电的。

公开(公告)号：US5433000A

公开(公告)日：1995-07-18

申请号：US210470

申请日：1994-03-21

Applicant: Toshio Tamura ,  Nobuyuki Yasuda

Inventor： Toshio Tamura ,  Nobuyuki Yasuda

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/4652 ,  H05K1/115 ,  H05K3/0044 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K3/429 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A multilayer wiring board is constructed of insulating substrates and circuit patterns formed thereon. A manufacturing method produces the multilayer wiring board by forming a mask on one surface of the multilayer substrate. The mask has apertures registered with blind holes and/or a through hole wherein the apertures have different diameters depending on the depths of the blind holes and/or the through hole such that the larger the depth, the larger the diameter. Etching is performed on the multilayer substrate corresponding to the smallest aperture using an abrasive powder having a particle size smaller than the diameter of the smallest aperture. Portions of the multilayer substrate are gradually etched corresponding to the other apertures using abrasive powders having particle sizes smaller than the diameters of the other apertures wherein the blind holes having the desired depths and/or the through hole are formed in the multilayer substrate. Accordingly, the blind holes having different depths and/or the through hole can be formed by using the single mask. Further, the required depths of the blind holes and/or the through hole can be obtained without unduly etching the bottom of the blind holes. A reliable electrical connection can be obtained between the circuit patterns in the different layers through the conductive films formed on the inner wall surfaces of the blind holes and/or the through hole.

Abstract translation: 多层布线板由绝缘基板和形成在其上的电路图案构成。 制造方法通过在多层基板的一个表面上形成掩模来制造多层布线板。 掩模具有与盲孔和/或通孔对齐的孔，其中孔根据盲孔和/或通孔的深度具有不同的直径，使得深度越大，直径越大。 使用粒径小于最小孔径直径的研磨粉末，在对应于最小孔径的多层基板上进行蚀刻。 使用具有小于其它孔径直径的研磨粉末，使用具有所需深度和/或通孔的盲孔​​形成在多层基板中的研磨粉末，逐渐蚀刻多层基板的部分。 因此，可以通过使用单个掩模来形成具有不同深度和/或通孔的盲孔​​。 此外，可以在不盲目蚀刻盲孔的底部的情况下获得盲孔和/或通孔所需的深度。 通过形成在盲孔和/或通孔的内壁表面上的导电膜，可以在不同层中的电路图案之间获得可靠的电连接。