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    THIN FILMS
    21.
    发明申请
    THIN FILMS 审中-公开
    薄膜

    公开(公告)号：US20110256718A1

    公开(公告)日：2011-10-20

    申请号：US13079562

    申请日：2011-04-04

    申请人： Suvi P. Haukka ,  Ivo Raaijmakers ,  Wei Min Li ,  Juhana Kostamo ,  Hessel Sprey ,  Christiaan J. Werkhoven

    发明人： Suvi P. Haukka ,  Ivo Raaijmakers ,  Wei Min Li ,  Juhana Kostamo ,  Hessel Sprey ,  Christiaan J. Werkhoven

    IPC分类号： H01L21/285

    CPC分类号： C23C16/029 ,  C23C16/34 ,  C23C16/401 ,  C23C16/403 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45534 ,  C30B25/14 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/3185 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2221/1089

    摘要： Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.

    摘要翻译： 通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。 在所示实施例中，在循环过程中引入了不同量的杂质源。 因此，即使对于非常薄的层也提供了梯度栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。 在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。 有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。 在一些实施例中，提供了额外的种子层或附加的过渡层。

    Silicon-on-insulator structures and methods
    22.
    发明授权
    Silicon-on-insulator structures and methods 有权
    绝缘体上硅结构和方法

    公开(公告)号：US07452757B2

    公开(公告)日：2008-11-18

    申请号：US10434423

    申请日：2003-05-07

    申请人： Christiaan J. Werkhoven ,  Ivo Raaijmakers ,  Chantal Arena

    发明人： Christiaan J. Werkhoven ,  Ivo Raaijmakers ,  Chantal Arena

    IPC分类号： H01L21/00

    CPC分类号： H01L21/31662 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3141 ,  H01L21/7624 ,  H01L21/76262

    摘要： Silicon-on-insulator (SOI) structures are provided by forming a single-crystal insulator over a substrate, followed by heteroepitaxy of a semiconductor layer thereover. Atomic layer deposition (ALD) is preferably used to form an amorphous insulator, followed by solid phase epitaxy to convert the layer into a single-crystal structure. Advantageously, the crystalline insulator has a lattice structure and lattice constant closely matching that of the semiconductor formed over it, and a ternary insulating material facilitates matching properties of the layers. Strained silicon can be formed without need for a buffer layer. An amorphous SiO2 layer can optionally be grown underneath the insulator. In addition, a buffer layer can be grown, either between the substrate and the insulator or between the insulator and the semiconductor layer, to produce desired strain in the active semiconductor layer.

    摘要翻译： 通过在衬底上形成单晶绝缘体，然后在其上进行异质外延半导体层来提供绝缘体上硅（SOI）结构。 原子层沉积（ALD）优选用于形成非晶绝缘体，随后进行固相外延将层转化为单晶结构。 有利地，结晶绝缘体具有与其上形成的半导体的晶格结构和晶格常数紧密匹配的晶格绝缘体，并且三元绝缘材料有助于层的匹配性质。 可以形成应变硅，而不需要缓冲层。 可以任选地在绝缘体下方生长非晶SiO 2层。 此外，可以在衬底和绝缘体之间或绝缘体和半导体层之间生长缓冲层，以在有源半导体层中产生期望的应变。

    Dielectric layers and methods of forming the same
    23.
    发明授权
    Dielectric layers and methods of forming the same 有权
    介电层及其形成方法

    公开(公告)号：US07323422B2

    公开(公告)日：2008-01-29

    申请号：US10379516

    申请日：2003-03-04

    申请人： Ivo Raaijmakers ,  Pekka J. Soininen ,  Jan Willem Maes

    发明人： Ivo Raaijmakers ,  Pekka J. Soininen ,  Jan Willem Maes

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L28/56 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： High dielectric constant (high-k) materials are formed directly over oxidation-susceptible conductors such as silicon. A discontinuous layer is formed, with gaps between grains of the high-k material. Exposed conductor underneath the grain boundaries is oxidized or nitridized to form, e.g., silicon dioxide or silicon nitride, when exposed to oxygen or nitrogen source gases at elevated temperatures. This dielectric growth is preferential underneath the grain boundaries such that any oxidation or nitridation at the interface between the high-k material grains and covered conductor is not as extensive. The overall dielectric constant of the composite film is high, while leakage current paths between grains is reduced. Ultrathin high-k materials with low leakage current are thereby enabled.

    摘要翻译： 高介电常数（高k）材料直接在氧化敏感导体（如硅）上形成。 形成不连续层，在高k材料的晶粒之间形成间隙。 在高温下暴露于氧或氮源气体时，在晶界之下的暴露导体被氧化或氮化以形成例如二氧化硅或氮化硅。 这种电介质生长优选在晶界之下，使得在高k材料晶粒和被覆导体之间的界面处的任何氧化或氮化不是很广泛。 复合膜的总介电常数高，而晶粒间的漏电流路径减小。 从而能够实现低泄漏电流的超薄高k材料。

    Method and apparatus of growing a thin film
    28.
    发明授权
    Method and apparatus of growing a thin film 有权

    公开(公告)号：US07060132B2

    公开(公告)日：2006-06-13

    申请号：US10270745

    申请日：2002-10-11

    申请人： Sven Lindfors ,  Ivo Raaijmakers

    发明人： Sven Lindfors ,  Ivo Raaijmakers

    IPC分类号： C30B23/00

    CPC分类号： C30B25/14 ,  C23C16/45502 ,  C23C16/45546 ,  C23C16/4583 ,  C30B25/02 ,  C30B25/08

    摘要： A method and apparatus for growing a thin film onto a substrate is disclosed. According to one embodiment, a plurality of substrates, each having a width and a length, are placed in a reaction space and the substrates are subjected to surface reactions of vapor-phase reactants according to the ALD method to form a thin film on the surfaces of the substrates. The reaction space comprises an elongated gas channel having a cross-section with a width greater that the height and which has a length which is at least 2 times greater than the length of one substrate in the direction of the gas flow in the channel, the channel having a folded configuration with at least one approximately 180 degree turn in the direction of the gas flow.

    Loadlock with integrated pre-clean chamber
    29.
    发明授权
    Loadlock with integrated pre-clean chamber 有权
    带集成预清洁室的负载锁定

    公开(公告)号：US07018504B1

    公开(公告)日：2006-03-28

    申请号：US09658784

    申请日：2000-09-11

    申请人： Ivo Raaijmakers ,  Ravinder Aggarwal ,  James Kusbel

    发明人： Ivo Raaijmakers ,  Ravinder Aggarwal ,  James Kusbel

    IPC分类号： C23F1/00 ,  H01L21/306 ,  C23C16/00

    CPC分类号： H01L21/67751 ,  H01L21/67167 ,  H01L21/67201 ,  H01L21/67757

    摘要： A wafer carrier adapted to hold a plurality of wafers and is positioned on an elevator plate in a load lock. The elevator plate is adapted to move between a first position with the carrier in a first chamber of the load lock and a second position with the carrier in the auxiliary chamber. In the second position, the elevator plate substantially seals the auxiliary chamber from the first chamber. In use, a first wafer is placed onto the wafer carrier. The wafer carrier can moved into the auxiliary chamber before or after the first wafer is placed onto the wafer carrier. The first wafer is auxiliary processed in the auxiliary chamber. A second wafer is placed onto the wafer carrier. Preferably after the second wafer is placed onto the wafer carrier, the first wafer is removed from the load lock. A third wafer is preferably then placed onto the wafer carrier so that the second wafer can cool. The second wafer is then removed from the load lock. The cycle is repeated.

    摘要翻译： 适于保持多个晶片并且位于加载锁中的电梯板上的晶片载体。 所述升降板适于在所述负载锁的第一室中的所述载体的第一位置和所述辅助室中的所述载体的第二位置之间移动。 在第二位置，升降板基本上将辅助室与第一室密封。 在使用中，将第一晶片放置在晶片载体上。 在将第一晶片放置在晶片载体上之前或之后，晶片载体可以移动到辅助室中。 第一个晶片在辅助室中辅助处理。 将第二晶片放置在晶片载体上。 优选地，在将第二晶片放置在晶片载体上之后，将第一晶片从负载锁上移除。 然后优选将第三晶片放置在晶片载体上，使得第二晶片可以冷却。 然后将第二个晶片从负载锁中取出。 重复循环。

    Apparatus for thermal treatment of substrates
    30.
    发明授权
    Apparatus for thermal treatment of substrates 失效
    基板热处理设备

    公开(公告)号：US06957690B1

    公开(公告)日：2005-10-25

    申请号：US09584656

    申请日：2000-05-30

    申请人： Ivo Raaijmakers

    发明人： Ivo Raaijmakers

    IPC分类号： C23C16/56 ,  F28F7/00 ,  H01L21/00

    CPC分类号： H01L21/67109

    摘要： Methods and apparatuses are provided for cooling semiconductor substrates prior to handling. In one embodiment, a substrate and support structure combination is lifted after high temperature processing to a cold wall of a thermal processing chamber, which acts as a heat sink. Conductive heat transfer across a small gap from the substrate to the heat sink speeds wafer cooling prior to handling the wafer (e.g., with a robot). In another embodiment, a separate plate is kept cool within a pocket during processing, and is moved close to the substrate and support after processing. In yet another embodiment, a cooling station between a processing chamber and a storage cassette includes two movable cold plates, which are movable to positions closely spaced on either side of the wafer.

    摘要翻译： 提供了用于在处理之前冷却半导体衬底的方法和装置。 在一个实施例中，将衬底和支撑结构组合在高温处理之后提升到用作散热器的热处理室的冷壁。 在从基板到散热片的小间隙处的导电热传递在处理晶片（例如，使用机器人）之前加速晶片冷却。 在另一个实施例中，单独的板在处理期间保持在袋内冷却，并且在处理之后移动靠近基板并支撑。 在另一个实施例中，处理室和存储盒之间的冷却站包括两个可移动的冷板，其可移动到在晶片的任一侧上紧密间隔开的位置。