公开(公告)号：US20130020720A1

公开(公告)日：2013-01-24

申请号：US13546163

申请日：2012-07-11

Applicant: Young Lyong Kim ,  Taehoon Kim ,  Jongho Lee ,  Chul-Yong Jang

Inventor： Young Lyong Kim ,  Taehoon Kim ,  Jongho Lee ,  Chul-Yong Jang

IPC: H01L25/07

CPC classification number: H01L21/76802 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24146 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

公开(公告)号：US20120266758A1

公开(公告)日：2012-10-25

申请号：US13446961

申请日：2012-04-13

Applicant: Jongho LEE ,  Jeahyuk Wie

Inventor： Jongho LEE ,  Jeahyuk Wie

IPC: G07F9/10

CPC classification number: F24C3/085 ,  F24C15/001 ,  F24C15/006 ,  F24C15/2007

Abstract: A cooker is provided. The cooker includes a casing, a cavity part in the casing and including a cooking chamber to cook food, and an exhaust duct through which exhaust gas is discharged. The exhaust duct includes a first duct part having a lower end communicating with the cooking chamber, a second duct part extending from the other end of the first duct part, the second duct part making a predetermined angle with respect to the first duct part or having a predetermined curvature, and a flow passage extension protruded from a portion of the first duct part or the second duct part in an outward direction. At least a portion of the flow passage extension extends at an angle different from the predetermined angle between the first and second duct parts or the flow passage extension has a curvature different from the predetermined curvature of the second duct part.

Abstract translation: 提供炊具。 炊具包括壳体，壳体中的空腔部分，并且包括用于烹饪食物的烹饪室以及排出废气的排气管。 排气管道包括具有与烹饪室连通的下端的第一管道部分，从第一管道部分的另一端延伸的第二管道部分，第二管道部分相对于第一管道部分形成预定角度或具有 预定的曲率以及从第一导管部或第二导管部的一部分向外方突出的流路延伸部。 流动通道延伸部分的至少一部分以与第一和第二管道部分之间的预定角度不同的角度延伸，或者流动通道延伸部具有不同于第二管道部分的预定曲率的曲率。

公开(公告)号：US20110272736A1

公开(公告)日：2011-11-10

申请号：US13102860

申请日：2011-05-06

Applicant: JONGHO LEE ,  Chang-Bong Oh ,  Ho Lee ,  Myungsun Kim

Inventor： JONGHO LEE ,  Chang-Bong Oh ,  Ho Lee ,  Myungsun Kim

IPC: H01L29/165

CPC classification number: H01L21/823807 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region.

Abstract translation: 半导体器件包括：衬底，包括第一区域和第二区域，每个区域具有n型区域和p型区域，其中第一区域中的n型区域包括硅沟道， 第一区域包括硅锗沟道，并且第二区域中的n型区域和p型区域分别包括硅沟道。 在第二区域中的n型和p型区域的基板上设置由热氧化物层形成的第一栅极绝缘图案。

公开(公告)号：US08029713B2

公开(公告)日：2011-10-04

申请号：US12244575

申请日：2008-10-02

Applicant: Jongho Lee

Inventor： Jongho Lee

IPC: B28B7/22

CPC classification number: B29C45/1635 ,  B29C45/27 ,  B29L2031/3005 ,  B60R13/0243

Abstract: A first mold has a core passage, and first and second cavities in fluid communication with each other at the core passage. A second mold has first and second nozzles therein that inject first and second resins to the first and second cavities, respectively. The core member is slidable within the core passage to provide or block the fluid communication between the cavities, and has a third nozzle therein to inject a third resin to the core passage. The first and second resins are injected into the cavities. The core member is moved to block the fluid communication between the cavities, before injecting the first and second resins is completed. The third resin is injected while moving the core member to provide the fluid communication, after injecting the first and second resins is completed. The molds are separated, thereby yielding a single molded product, such as a vehicle door trim.

Abstract translation: 第一模具具有芯通道，并且在芯通道处彼此流体连通的第一和第二空腔。 第二模具在其中具有分别将第一和第二树脂注入到第一和第二空腔中的第一和第二喷嘴。 芯构件可在芯通道内滑动以提供或阻挡空腔之间的流体连通，并且其中具有第三喷嘴以将第三树脂注入到芯通道。 将第一和第二树脂注入到空腔中。 在完成注入第一和第二树脂之前，移动芯构件以阻止空腔之间的流体连通。 在移动芯部件以提供流体连通时注入第三树脂，在完成注入第一和第二树脂之后。 模具被分离，从而产生单个模制产品，例如车门装饰件。

公开(公告)号：US20100096754A1

公开(公告)日：2010-04-22

申请号：US12588477

申请日：2009-10-16

Applicant: Jonggi Lee ,  SunWon Kang ,  Young Lyong Kim ,  Jongho Lee ,  Chul-Yong Jang ,  Minill Kim ,  Eunchul Ahn ,  Kwang Yong Lee ,  Seungduk Baek ,  Ji-Seok Hong

Inventor： Jonggi Lee ,  SunWon Kang ,  Young Lyong Kim ,  Jongho Lee ,  Chul-Yong Jang ,  Minill Kim ,  Eunchul Ahn ,  Kwang Yong Lee ,  Seungduk Baek ,  Ji-Seok Hong

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/13 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/06 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/1191 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line.

Abstract translation: 提供半导体封装，半导体模块和制造半导体封装的方法。 该方法提供了包括接合焊盘的衬底。 该方法形成用于使衬底上的焊盘露出的介电层。 该方法形成在电介质层上电连接到接合焊盘的再分配线。 该方法形成外部端子，该外部端子电连接到接合焊盘，而不使用在再分配线上限制外部端子的位置的焊接掩模。

公开(公告)号：US20100072593A1

公开(公告)日：2010-03-25

申请号：US12586565

申请日：2009-09-24

Applicant: Young Lyong Kim ,  Jongho Lee ,  Cheul-Joong Youn ,  Eunchul Ahn

Inventor： Young Lyong Kim ,  Jongho Lee ,  Cheul-Joong Youn ,  Eunchul Ahn

IPC: H01L23/495

CPC classification number: H01L23/49827 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first package including at least one first semiconductor chip; a second package including an external connection terminal and at least one second semiconductor chip, the second package being stacked on the first package; and an interposer disposed between the first and second packages and connected to the external connection terminal to electrically connect the first and second packages to each other. The interposer comprises an intermediate connector having an exposed end portion to which the second package is electrically connected via the external connection terminal and a protruding end portion lower than the exposed end portion to which the first package is electrically connected.

Abstract translation: 半导体封装包括包括至少一个第一半导体芯片的第一封装; 包括外部连接端子和至少一个第二半导体芯片的第二封装，所述第二封装堆叠在所述第一封装上; 以及设置在第一和第二封装之间并且连接到外部连接端子以将第一和第二封装彼此电连接的插入器。 插入器包括具有暴露端部的中间连接器，第二封装经由外部连接端子电连接到该外部端部，以及比第一封装电连接到的暴露端部低的突出端部。

公开(公告)号：US07112539B2

公开(公告)日：2006-09-26

申请号：US10999608

申请日：2004-11-29

Applicant: Jongho Lee ,  Nae-In Lee

Inventor： Jongho Lee ,  Nae-In Lee

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.

公开(公告)号：US09343437B2

公开(公告)日：2016-05-17

申请号：US14680094

申请日：2015-04-07

Applicant: Ae-nee Jang ,  Jin-Woo Park ,  Seokhyun Lee ,  Jongho Lee

Inventor： Ae-nee Jang ,  Jin-Woo Park ,  Seokhyun Lee ,  Jongho Lee

IPC: H01L23/10 ,  H01L25/065 ,  H01L23/373 ,  H01L23/367 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/528 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor package devices and methods of forming the semiconductor package devices are provided. The semiconductor package devices may include a lower package including a lower semiconductor chip on a lower substrate, an upper package including an upper semiconductor chip on an upper substrate. The upper substrate may include a protruding part corresponding to the lower semiconductor chip and a connection part that has a bottom surface lower than a bottom surface of the protruding part and is disposed around the protruding part. The semiconductor package devices may also include a heat dissipation part in a space between the lower semiconductor chip and the protruding part on the upper substrate and a package connection pattern electrically connecting the lower package to the upper package.

Abstract translation: 提供半导体封装器件和形成半导体封装器件的方法。 半导体封装器件可以包括下封装，其包括在下基板上的下半导体芯片，在上基板上包括上半导体芯片的上封装。 上基板可以包括对应于下半导体芯片的突出部分和具有低于突出部分的底表面的底表面并且布置在突出部分周围的连接部分。 半导体封装器件还可以包括在下半导体芯片和上基板上的突出部分之间的空间中的散热部分和将下封装电连接到上封装的封装连接图案。

公开(公告)号：US20160005714A1

公开(公告)日：2016-01-07

申请号：US14682113

申请日：2015-04-09

Applicant: SEOKHYUN LEE ,  Chul-Yong JANG ,  JONGHO LEE

Inventor： SEOKHYUN LEE ,  Chul-Yong JANG ,  JONGHO LEE

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/29036 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括具有安装有下半导体芯片的第一封装衬底的第一封装和具有安装有上半导体芯片的第二封装衬底的第二封装。 第二封装衬底包括其上安装有上半导体芯片的芯片区域和设置在其周围的连接区域。 芯片区域包括限定第一凹陷区域的第一表面和限定第一突出部分的第二表面。 上半导体芯片安装在第二表面的相对边缘上并且彼此间隔开以具有朝向芯片区域之外的连接区域突出的部分。

公开(公告)号：US08482077B2

公开(公告)日：2013-07-09

申请号：US13102860

申请日：2011-05-06

Applicant: Jongho Lee ,  Chang-Bong Oh ,  Ho Lee ,  Myungsun Kim

Inventor： Jongho Lee ,  Chang-Bong Oh ,  Ho Lee ,  Myungsun Kim

IPC: H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region.

Abstract translation: 半导体器件包括：衬底，包括第一区域和第二区域，每个区域具有n型区域和p型区域，其中第一区域中的n型区域包括硅沟道， 第一区域包括硅锗沟道，并且第二区域中的n型区域和p型区域分别包括硅沟道。 在第二区域中的n型和p型区域的基板上设置由热氧化物层形成的第一栅极绝缘图案。