公开(公告)号：US11227825B2

公开(公告)日：2022-01-18

申请号：US15773030

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/03 ,  H05K1/16 ,  H01F17/00 ,  H01F17/06 ,  H01L21/02 ,  H01L21/50 ,  H01L21/60 ,  H01L23/48 ,  H01L23/60 ,  G11B5/17 ,  G11B5/31 ,  G11B5/147 ,  G11B5/187 ,  H01L23/498 ,  H01F27/40 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01G4/33 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US11101222B2

公开(公告)日：2021-08-24

申请号：US16326679

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta ,  Javier Soto Gonzalez ,  Kwangmo Lim

IPC: H01L23/538 ,  H01L23/00

Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

公开(公告)号：US20210066232A1

公开(公告)日：2021-03-04

申请号：US17098754

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Sri Ranga Sai Boyapati ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Javier Soto Gonzalez ,  Kwangmo Chris Lim ,  Aleksandar Aleksov

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/13 ,  H01L21/48

Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.

公开(公告)号：US20190259705A1

公开(公告)日：2019-08-22

申请号：US16335845

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Henning Braunisch ,  Krishna Bharath ,  Javier Soto Gonzalez ,  Javier A. Falcon

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

公开(公告)号：US10327330B2

公开(公告)日：2019-06-18

申请号：US15762791

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Javier Soto Gonzalez ,  Dilan Seneviratne ,  Shruti R. Jaywant ,  Sashi S. Kandanur ,  Srinivas Pietambaram ,  Nadine L. Dabby ,  Braxton Lathrop ,  Rajat Goyal ,  Vivek Raghunathan

IPC: H05K1/02 ,  H01L23/14 ,  H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/18 ,  H05K3/28 ,  H05K3/34 ,  H05K3/42 ,  H05K3/46 ,  H05K3/20

Abstract: Some forms relate to an example stretchable electronic assembly. The stretchable electronic assembly includes a stretchable body that includes electronic components. A plurality of meandering conductors electrically connect the electronic components. The plurality of meandering conductors may be exposed from the stretchable body. A plurality of conductive pads are electrically connected to at least one of the electronic components or some of the plurality of meandering conductors. The plurality of conductive pads may be exposed from the stretchable body. The stretchable body includes an upper surface and lower surface. The plurality of meandering conductors may be exposed from the lower surface (in addition to, or alternatively to, the upper surface) of the stretchable body.

公开(公告)号：US20170344055A1

公开(公告)日：2017-11-30

申请号：US15164559

申请日：2016-05-25

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Javier Soto Gonzalez

IPC: G06F1/16 ,  H05K1/03 ,  H05K3/32 ,  H05K1/18 ,  H05K3/22 ,  H05K1/02

CPC classification number: G06F1/163 ,  H01L23/5387 ,  H05K1/0281 ,  H05K1/0283 ,  H05K1/0296 ,  H05K1/0393 ,  H05K1/185 ,  H05K3/22 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/0133 ,  H05K2201/09118 ,  H05K2201/09263 ,  H05K2201/10522 ,  H05K2201/2009 ,  H05K2203/1316 ,  H05K2203/1327

Abstract: An electronic circuit may include an elastomeric substrate with an electronic die attached to the elastomer substrate at a first substrate area and one or more meander traces electrically coupled to the electronic die and encapsulated in the elastomer substrate at a second substrate area that is adjacent to the first substrate area. An inelastic, non-electronic, structural brace may be attached to the elastomeric substrate in the first substrate area.

公开(公告)号：US09780054B2

公开(公告)日：2017-10-03

申请号：US14529881

申请日：2014-10-31

Applicant: INTEL CORPORATION

Inventor： John S. Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K Nalla

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L25/03 ,  H01L25/10 ,  H05K1/18 ,  H01L21/768 ,  H01L25/07 ,  H01L23/31 ,  H01L25/11 ,  H05K3/46

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

公开(公告)号：US09716084B2

公开(公告)日：2017-07-25

申请号：US15208502

申请日：2016-07-12

Applicant: INTEL CORPORATION

Inventor： Digvijay A. Raorane ,  Yonggang Li ,  Rahul N. Manepalli ,  Javier Soto Gonzalez

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683 ,  H01L23/522 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/8385 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/40501 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US09257380B2

公开(公告)日：2016-02-09

申请号：US14624873

申请日：2015-02-18

Applicant: Intel Corporation

Inventor： Ravi K. Nalla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56 ,  H01L21/02 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

公开(公告)号：US20150171067A1

公开(公告)日：2015-06-18

申请号：US14636016

申请日：2015-03-02

Applicant: INTEL CORPORATION

Inventor： Digvijay A. Raorane ,  Yonggang Li ,  Rahul N. Manepalli ,  Javier Soto Gonzalez

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/8385 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/40501 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及具有多个管芯的三维（3D）集成的集成电路（IC）封装组件，以及包含这种3D IC封装组件的相应制造方法和系统。 可以在诸如微处理器管芯的第一管芯上形成无凸起的堆积层（BBUL）封装衬底。 可以使用激光辐射在模具背面膜中形成开口，以暴露第一裸片背面的TSV焊盘。 诸如存储器管芯堆叠的第二管芯可以通过在第一和第二管芯的对应TSV之间形成的管芯互连而耦合到第一管芯。 可以施加底部填充材料以填充第一和第二管芯之间的任何剩余间隙中的一些或全部，和/或可以在第二管芯和/或封装衬底上施加密封剂。 可以描述和/或要求保护其他实施例。