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公开(公告)号:US20130062760A1
公开(公告)日:2013-03-14
申请号:US13228244
申请日:2011-09-08
申请人: Jui-Pin Hung , Jing-Cheng Lin , Nai-Wei Liu , Chin-Chuan Chang , Chen-Hua Yu , Shin-Puu Jeng , Chin-Fu Kao , Yi-Chao Mao , Szu Wei Lu
发明人: Jui-Pin Hung , Jing-Cheng Lin , Nai-Wei Liu , Chin-Chuan Chang , Chen-Hua Yu , Shin-Puu Jeng , Chin-Fu Kao , Yi-Chao Mao , Szu Wei Lu
IPC分类号: H01L23/498 , H01L21/60 , H01L21/56
CPC分类号: H01L21/561 , H01L21/568 , H01L21/6836 , H01L23/147 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/81 , H01L24/96 , H01L24/97 , H01L2221/68345 , H01L2221/68359 , H01L2221/68377 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05099 , H01L2224/05569 , H01L2224/05572 , H01L2224/05599 , H01L2224/11002 , H01L2224/12105 , H01L2224/13022 , H01L2224/16225 , H01L2224/16227 , H01L2224/73267 , H01L2224/83191 , H01L2224/96 , H01L2224/97 , H01L2924/00014 , H01L2924/12042 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/3511 , H01L2224/11 , H01L2224/81 , H01L2224/05552 , H01L2924/00
摘要: Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated.
摘要翻译: 公开了利用新颖的芯片附着膜的半导体器件的封装方法和结构。 在一个实施例中,封装半导体器件的方法包括提供载体晶片并且在载体晶片上形成包括聚合物的管芯附着膜(DAF)。 多个模具附接到DAF,并且多个管芯被封装。 至少载体晶片从封装的管芯移除,并且封装的管芯被切割。
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公开(公告)号:US09960088B2
公开(公告)日:2018-05-01
申请号:US13290879
申请日:2011-11-07
申请人: Yi-Chao Mao , Jui-Pin Hung , Jing-Cheng Lin , Shin-Puu Jeng , Chen-Hua Yu
发明人: Yi-Chao Mao , Jui-Pin Hung , Jing-Cheng Lin , Shin-Puu Jeng , Chen-Hua Yu
IPC分类号: B24B49/10 , H01L21/66 , B24B37/013 , B24B7/22 , H01L23/31
CPC分类号: H01L22/26 , B24B7/228 , B24B37/013 , B24B49/10 , H01L22/12 , H01L23/3114 , H01L2924/0002 , H01L2924/00
摘要: A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity.
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公开(公告)号:US20130203215A1
公开(公告)日:2013-08-08
申请号:US13369083
申请日:2012-02-08
申请人: Jui-Pin Hung , Jing-Cheng Lin
发明人: Jui-Pin Hung , Jing-Cheng Lin
IPC分类号: H01L21/56
CPC分类号: H01L24/97 , H01L21/4853 , H01L21/486 , H01L21/563 , H01L21/568 , H01L21/78 , H01L23/3128 , H01L23/3185 , H01L24/11 , H01L24/19 , H01L24/94 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/16235 , H01L2224/32145 , H01L2224/73204 , H01L2224/73259 , H01L2224/92224 , H01L2224/94 , H01L2224/97 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00 , H01L2224/83
摘要: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.
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公开(公告)号:US20130087951A1
公开(公告)日:2013-04-11
申请号:US13270957
申请日:2011-10-11
申请人: Jing-Cheng Lin , Hsien-Wen Liu , Jui-Pin Hung , Shin-Puu Jeng , Chen-Hua Yu
发明人: Jing-Cheng Lin , Hsien-Wen Liu , Jui-Pin Hung , Shin-Puu Jeng , Chen-Hua Yu
CPC分类号: B29C35/0805 , B29C2035/0855 , H01L21/565 , H05B6/6491 , H05B6/806
摘要: An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component.
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公开(公告)号:US20130075892A1
公开(公告)日:2013-03-28
申请号:US13246553
申请日:2011-09-27
申请人: Jing-Cheng Lin , Weng-Jin Wu , Ying-Ching Shih , Jui-Pin Hung , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu
发明人: Jing-Cheng Lin , Weng-Jin Wu , Ying-Ching Shih , Jui-Pin Hung , Szu Wei Lu , Shin-Puu Jeng , Chen-Hua Yu
CPC分类号: H01L23/48 , H01L21/6835 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L2221/68327 , H01L2224/0401 , H01L2224/05009 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2224/97 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2924/3511 , H01L2924/00012 , H01L2224/81 , H01L2924/00 , H01L2224/83
摘要: A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.
摘要翻译: 一种用于制造三维集成电路的方法包括:提供其中多个半导体管芯安装在第一半导体管芯上的晶片堆叠,在第一半导体管芯的第一侧上形成模塑料层,其中多个半导体管芯被嵌入 在模塑料层中。 该方法还包括研磨第一半导体管芯的第二面直到多个通孔露出,将晶片堆叠附着到带框架上并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。
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公开(公告)号:US20130001776A1
公开(公告)日:2013-01-03
申请号:US13170973
申请日:2011-06-28
申请人: Chen-Hua Yu , Jing-Cheng Lin , Nai-Wei Liu , Jui-Pin Hung , Shin-Puu Jeng
发明人: Chen-Hua Yu , Jing-Cheng Lin , Nai-Wei Liu , Jui-Pin Hung , Shin-Puu Jeng
IPC分类号: H01L23/485 , H01L21/28
CPC分类号: H01L21/4853 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L23/49838 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05569 , H01L2224/05572 , H01L2224/12105 , H01L2224/13022 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/73267 , H01L2224/94 , H01L2224/96 , H01L2924/00014 , H01L2924/01029 , H01L2924/0132 , H01L2924/014 , H01L2924/181 , H01L2224/19 , H01L2224/11 , H01L2224/03 , H01L2224/05552 , H01L2924/00 , H01L2224/214
摘要: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.
摘要翻译: 封装包括具有基板的器件裸片。 模塑料与基材的侧壁接触。 金属焊盘在基板上。 钝化层具有覆盖金属焊盘的边缘部分的部分。 金属支柱已经过去并与金属垫接触。 介电层位于钝化层的上方。 由模塑料或聚合物形成的包装材料在电介质层的上面。 电介质层包括位于钝化层和封装材料之间的底部,以及在金属柱的侧壁和封装材料的侧壁之间的侧壁部分。 聚合物层在包装材料,模塑料和金属支柱之上。 后钝化互连(PPI)延伸到聚合物层中。 焊球在PPI上方,并通过PPI电耦合到金属焊盘。
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公开(公告)号:US09153506B2
公开(公告)日:2015-10-06
申请号:US13542896
申请日:2012-07-06
申请人: Chien Rhone Wang , Kewei Zuo , Chen-Hua Yu , Jing-Cheng Lin , Yen-Hsin Liu
发明人: Chien Rhone Wang , Kewei Zuo , Chen-Hua Yu , Jing-Cheng Lin , Yen-Hsin Liu
IPC分类号: G06F19/00 , H01L21/66 , H01L21/768
CPC分类号: H01L22/20 , H01L21/76898 , H01L22/12
摘要: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.
摘要翻译: 本公开提供了用于形成具有一个或多个贯穿硅通孔(TSV)特征的IC结构的集成电路(IC)制造方法的一个实施例。 IC制作方法包括执行多个处理步骤; 从多个处理步骤收集物理计量数据; 基于所述物理测量数据从所述多个处理步骤收集虚拟测量数据; 基于物理测量数据和虚拟测量数据,为IC结构生成产量预测; 以及基于所述产量预测在较早的处理步骤中识别动作。
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公开(公告)号:US09006004B2
公开(公告)日:2015-04-14
申请号:US13429054
申请日:2012-03-23
申请人: Jing-Cheng Lin , Szu Wei Lu
发明人: Jing-Cheng Lin , Szu Wei Lu
IPC分类号: H01L21/66 , H01L21/683 , H01L23/00 , H01L25/065 , H01L25/00 , H01L21/56
CPC分类号: H01L25/0655 , H01L21/563 , H01L21/6835 , H01L22/14 , H01L23/3157 , H01L23/49827 , H01L23/49838 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/18 , H01L25/50 , H01L2221/68345 , H01L2224/11 , H01L2224/11002 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13155 , H01L2224/13184 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16238 , H01L2224/1703 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81 , H01L2224/81005 , H01L2224/81191 , H01L2224/81801 , H01L2224/81895 , H01L2224/83 , H01L2224/83104 , H01L2224/9202 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2924/15311 , H01L2924/00
摘要: A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.
摘要翻译: 一种方法包括将第一包装部件接合在第二包装部件的第一表面上,并且从第二包装部件的第二表面探测第一包装部件和第二包装部件。 通过探测第二包装部件的第二表面上的连接器来进行探测步骤。 连接器连接到第一包装部件。 在探测步骤之后,在第二包装部件的第一表面上结合第三包装部件。
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公开(公告)号:US08803316B2
公开(公告)日:2014-08-12
申请号:US13311692
申请日:2011-12-06
申请人: Yung-Chi Lin , Hsin-Yu Chen , Wen-Chih Chiou , Ku-Feng Yang , Tsang-Jiuh Wu , Jing-Cheng Lin
发明人: Yung-Chi Lin , Hsin-Yu Chen , Wen-Chih Chiou , Ku-Feng Yang , Tsang-Jiuh Wu , Jing-Cheng Lin
IPC分类号: H01L23/48
CPC分类号: H01L23/49827 , H01L21/76879 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05556 , H01L2224/05558 , H01L2224/0557 , H01L2224/11011 , H01L2224/13025 , H01L2224/131 , H01L2224/1405 , H01L2224/14104 , H01L2224/73204 , H01L2924/01028 , H01L2924/0132 , H01L2924/067 , H01L2924/0705 , H01L2924/181 , H01L2924/00 , H01L2924/014 , H01L2924/00012
摘要: A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.
摘要翻译: 一种器件包括具有正面和背面的衬底,从衬底的背面延伸到前侧的通孔,以及位于衬底的背面和通孔上方的导电焊盘。 导电垫具有基本平坦的顶表面。 导电凸块在基本上平坦的顶表面上方具有非平面的顶表面,并且与通孔对准。 导电凸块和导电垫由相同的材料形成。 在导电凸块和导电垫之间不形成界面。
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公开(公告)号:US08796833B2
公开(公告)日:2014-08-05
申请号:US13572302
申请日:2012-08-10
申请人: Jung-Hua Chang , Cheng-Lin Huang , Jing-Cheng Lin
发明人: Jung-Hua Chang , Cheng-Lin Huang , Jing-Cheng Lin
IPC分类号: H01L23/495
摘要: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.
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