公开(公告)号：US08729590B2

公开(公告)日：2014-05-20

申请号：US13870740

申请日：2013-04-25

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Tongbi Jiang

IPC: H01L33/00

CPC classification number: H01L33/10 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/46

Abstract: Solid state lighting devices having side reflectivity and associated methods of manufacturing are disclosed herein. In one embodiment, a method of forming a solid state lighting device includes attaching a solid state emitter to a support substrate, mounting the solid state emitter and support substrate to a temporary carrier, and cutting kerfs through the solid state emitter and the substrate to separate individual dies. The solid state emitter can have a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The individual dies can have sidewalls that expose the first semiconductor material, active region and second semiconductor material. The method can further include applying a reflective material into the kerfs and along the sidewalls of the individual dies.

Abstract translation: 本文公开了具有侧反射率和相关制造方法的固态照明装置。 在一个实施例中，形成固态照明装置的方法包括将固态发射器附接到支撑衬底，将固态发射器和支撑衬底安装到临时载体上，以及通过固态发射器和衬底切割缝隙以分离 个人死亡 固态发射器可以具有第一半导体材料，第二半导体材料和第一和第二半导体材料之间的有源区。 各个管芯可以具有露出第一半导体材料，有源区和第二半导体材料的侧壁。 该方法还可以包括将反射材料施加到切口中并且沿着各个模具的侧壁。

公开(公告)号：US20140042618A1

公开(公告)日：2014-02-13

申请号：US14055993

申请日：2013-10-17

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Don L. Yates ,  Yangyang Sun

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L23/49811 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76828 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/48 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/03464 ,  H01L2224/03472 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2224/05552

Abstract: Methods of forming a Ni material on a bond pad are disclosed. The methods include forming a dielectric material over a bond pad, forming an opening within the dielectric material to expose the bond pad, curing the dielectric material to form a surface of the dielectric material having a steep curvilinear profile, and forming a nickel material over the at least one bond pad. The dielectric material having a steep curvilinear profile may be formed by altering at least one of a curing process of the dielectric material and a thickness of the dielectric material. The dielectric material may be used to form a relatively thick Ni material on bond pads smaller than about 50 μm. Semiconductor structures formed by such methods are also disclosed.

Abstract translation: 公开了在接合焊盘上形成Ni材料的方法。 所述方法包括在接合焊盘上形成电介质材料，在电介质材料内形成开口以露出接合焊盘，固化电介质材料以形成具有陡峭曲线轮廓的电介质材料的表面，并在 至少一个键盘。 可以通过改变介电材料的固化过程和电介质材料的厚度中的至少一个来形成具有陡峭曲线轮廓的电介质材料。 电介质材料可用于在小于约50μm的接合焊盘上形成相对较厚的Ni材料。 还公开了通过这些方法形成的半导体结构。

公开(公告)号：US20130309861A1

公开(公告)日：2013-11-21

申请号：US13952481

申请日：2013-07-26

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L21/768

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

公开(公告)号：US11776877B2

公开(公告)日：2023-10-03

申请号：US17335994

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/44 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L25/065 ,  H01L23/373 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L23/44 ,  H01L21/50 ,  H01L21/52 ,  H01L21/54 ,  H01L21/563 ,  H01L23/04 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/3736 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L24/29 ,  H01L24/33 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/133 ,  H01L2224/13025 ,  H01L2224/1329 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29191 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8388 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/156 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2224/29191 ,  H01L2924/0715 ,  H01L2224/2929 ,  H01L2924/00014 ,  H01L2224/29393 ,  H01L2924/01006 ,  H01L2224/2939 ,  H01L2924/014 ,  H01L2224/83447 ,  H01L2924/00014 ,  H01L2224/83424 ,  H01L2924/00014 ,  H01L2224/1134 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2224/1329 ,  H01L2924/00014 ,  H01L2224/133 ,  H01L2924/00014 ,  H01L2224/16145 ,  H01L2924/00012 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/83101 ,  H01L2924/00014 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US20200350224A1

公开(公告)日：2020-11-05

申请号：US16936639

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L23/36 ,  H01L25/00 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H01L23/373 ,  H01L23/42

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10748878B2

公开(公告)日：2020-08-18

申请号：US16523804

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Jaspreet S. Gandhi ,  James M. Derderian

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/40 ,  H01L23/367 ,  H01L23/00 ,  H01L21/78 ,  H01L25/18 ,  H01L23/538

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

公开(公告)号：US10741460B2

公开(公告)日：2020-08-11

申请号：US16162195

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC: H01L21/66 ,  H01L23/00

Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US10651155B2

公开(公告)日：2020-05-12

申请号：US16122280

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L21/768

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

公开(公告)号：US10573612B2

公开(公告)日：2020-02-25

申请号：US16104720

申请日：2018-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/34 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

公开(公告)号：US20190393050A1

公开(公告)日：2019-12-26

申请号：US16561906

申请日：2019-09-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  Dale Arnold

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  C23C18/32

Abstract: Apparatuses and methods for formation of a bond site including an opening with a discontinuous profile are disclosed herein. An example apparatus may at least include a substrate, a contact on the substrate, and a mask layer formed on the substrate and at least a portion of the contact. The mask layer may also include an opening formed therein, with the opening having a discontinuous profile from a top surface of the mask layer to the contact.