公开(公告)号：US07385412B2

公开(公告)日：2008-06-10

申请号：US11409060

申请日：2006-04-24

申请人： Salman Akram ,  William M. Hiatt ,  Alan G. Wood ,  Charles M. Watkins ,  Kyle K. Kirby

发明人： Salman Akram ,  William M. Hiatt ,  Alan G. Wood ,  Charles M. Watkins ,  Kyle K. Kirby

IPC分类号： G01R31/02 ,  G01R31/26 ,  H01L27/00

CPC分类号： G01R31/2635 ,  G01R31/2831

摘要： Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.

摘要翻译： 本文公开了用于测试微电子成像器和微特征器件的系统和方法。 在一个实施例中，一种方法包括提供微功能工件，其包括具有正面，背面和多个微电子管芯的衬底。 各个管芯包括集成电路和在衬底的背面可操作地耦合到集成电路的多个接触焊盘。 该方法包括使各个接触垫与探针卡的相应引脚接触。 该方法还包括测试模具。 在另一个实施例中，各个管芯还可以包括在衬底的前侧的图像传感器，并可操作地耦合到集成电路。 在测试模具时，图像传感器被照亮。

公开(公告)号：US20080119038A1

公开(公告)日：2008-05-22

申请号：US12024712

申请日：2008-02-01

申请人： Warren Farnworth ,  Salman Akram

发明人： Warren Farnworth ,  Salman Akram

IPC分类号： H01L21/44

CPC分类号： H05K3/321 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/12 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12044 ,  H01L2924/14 ,  H05K3/244 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/10984 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00012

摘要： An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.

摘要翻译： 提供了一种用于在镀钯触点上形成具有钯金属层的衬底的方法，该衬底在衬底的至少一个接触点上并具有柔性导电聚合物凸块，优选两级环氧树脂。 本发明还涉及包括一个或多个这些基底的组件。

公开(公告)号：US07368812B2

公开(公告)日：2008-05-06

申请号：US11249540

申请日：2005-10-13

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： H01L23/02

CPC分类号： H01L23/3114 ,  G01R1/07314 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49169 ,  H01L2224/05552 ,  H01L2924/00

摘要： A carrier substrate, or interposer, for use in a chip-scale package includes a material, such as a semiconductive material, that has a coefficient of thermal expansion that is the same or similar to that of the semiconductor device to be secured thereto. The interposer may also include a rerouting element laminated over the remainder of the interposer and including one or more dielectric layers, as well as a conductive layer for rerouting the bond pad locations of a semiconductor device with which the interposer is to be assembled. The interposers may be fabricated on a “wafer scale.” Accordingly, a semiconductor device assembly may include a first, semiconductor device-carrying substrate and a second, interposer-comprising substrate. Regions of the second substrate that comprise the boundaries between adjacent interposers may be thinner than other regions of the second substrate, including the regions from which the interposers are formed.

摘要翻译： 用于芯片级封装的载体衬底或插入件包括诸如半导体材料的材料，其具有与要固定的半导体器件相同或相似的热膨胀系数。 插入器还可以包括层压在插入件的其余部分上并且包括一个或多个电介质层的重新布线元件，以及用于重新路由将要组装中介层的半导体器件的接合焊盘位置的导电层。 内插器可以在“晶片尺度”上制造。 因此，半导体器件组件可以包括第一半导体器件承载衬底和包括第二插入件的衬底。 包括相邻插入件之间的边界的第二衬底的区域可以比第二衬底的其它区域薄，包括形成有插入层的区域。

公开(公告)号：US20080054386A1

公开(公告)日：2008-03-06

申请号：US11513246

申请日：2006-08-31

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： H01L31/0232 ,  H01L21/00

CPC分类号： H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687

摘要： A recessed color filter array using patterned metal as an etch stop and a method of forming the same. In one embodiment, at least one metal etch stop is formed in a semiconductor dielectric layer at the same time as the formation of one or more layers of metal interconnect elements, thereby reducing the number of necessary process steps and reducing costs. The etch stop may be formed at any layer where other metal elements are present.

摘要翻译： 使用图案化金属作为蚀刻停止件的凹陷式滤色器阵列及其形成方法。 在一个实施例中，在形成一层或多层金属互连元件的同时，在半导体介电层中形成至少一个金属蚀刻停止层，从而减少必要的工艺步骤的数量并降低成本。 蚀刻停止件可以形成在存在其它金属元件的任何层。

公开(公告)号：US07327016B2

公开(公告)日：2008-02-05

申请号：US10910676

申请日：2004-08-03

申请人： Leonard Forbes ,  Kie Y. Ahn ,  Salman Akram

发明人： Leonard Forbes ,  Kie Y. Ahn ,  Salman Akram

IPC分类号： H01L39/00

CPC分类号： G11C7/02 ,  G11C7/18 ,  H01L23/5225 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： An electronic system is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.

摘要翻译： 电子系统具有用于改善集成电路上的传输线操作的结构。 用于传输线操作的结构包括在衬底上的第一层导电材料。 第一层绝缘材料形成在导电材料的第一层上。 在第一绝缘材料层上形成多个高磁导率金属线。 高渗透性金属线的数量包括复合六铁氧体膜。 多个传输线形成在第一绝缘材料层上并且与高磁导率金属线平行。 在传输线和一对高导磁性金属线上形成第二层绝缘材料。 用于传输线操作的结构包括在第二绝缘材料层上的第二层导电材料。

公开(公告)号：US20070262463A1

公开(公告)日：2007-11-15

申请号：US11585655

申请日：2006-10-24

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： H01L23/488 ,  H01L21/4763

CPC分类号： H01L23/49811 ,  G01R1/0408 ,  G01R1/0466 ,  G01R1/0483 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1403 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H05K1/112

摘要： The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls on a die, partial wafer or wafer under test for testing and burn-in. The interconnections are formed in recesses sized and shaped to receive and contain approximately 10% to 50%, and preferably about 30%, of the total height of each solder ball within its associated interconnection. Such a design compensates for under-sized or misshapen solder balls on the die under test and thereby prevents a possible false failure indication for the die under test. This design also distributes the forces on the solder ball caused by biasing the die under test to its temporary package to the periphery of the solder ball and thus reduces the likelihood of damage to the solder ball or the semiconductor substrate.

摘要翻译： 本发明涉及一种用于形成用于临时封装的互连的方法，其中所述互连能够接收待测的芯片上的焊球，用于测试和老化的部分晶片或晶片。 互连形成在尺寸和形状上的凹部中，以容纳并容纳其相关联的互连中每个焊球的总高度的约10％至5​​0％，优选约30％。 这样的设计补偿了被测试模具上的尺寸不均匀或错位的焊球，从而防止了被测试模具的可能的虚假故障指示。 该设计还通过将被测试的模具偏置到其临时封装到焊球的周边而将焊球上的力分布，从而降低了焊球或半导体衬底的损坏的可能性。

公开(公告)号：US07282794B2

公开(公告)日：2007-10-16

申请号：US11302304

申请日：2005-12-13

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： H01L23/02

CPC分类号： H01L25/18 ,  H01L23/3185 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed.

摘要翻译： 公开了使用间隔元件以允许增加器件密度和增加半导体器件的热传导或散热的堆叠结构的多个集成电路器件及其堆叠方法。

公开(公告)号：US07259578B2

公开(公告)日：2007-08-21

申请号：US11389794

申请日：2006-03-27

申请人： Salman Akram ,  Alan G. Wood

发明人： Salman Akram ,  Alan G. Wood

IPC分类号： G01R31/02

CPC分类号： G01R1/0735 ,  G01R1/0425 ,  G01R1/0483 ,  G01R1/07342 ,  G01R3/00 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81899 ,  H01L2924/00014 ,  H05K3/326 ,  H01L2224/05599

摘要： A test system for testing semiconductor components includes an interconnect having a substrate and contacts on the substrate for electrically engaging terminal contacts on the components. The interconnect also includes one or more cavities in the substrate which form flexible segments proximate to the interconnect contacts. The flexible segments permit the interconnect contacts to move independently in the z-direction to accommodate variations in the height and planarity of the terminal contacts. In addition, the cavities can be pressurized, or alternately filled with a polymer material, to adjust a compliancy of the flexible segments. Different embodiments of the interconnect contacts include: metallized recesses for retaining the terminal contacts, metallized projections for penetrating the terminal contacts, metallized recesses with penetrating projections, and leads contained on a polymer tape and cantilevered over metallized recesses. The test system can be configured for testing wafer sized components, such as wafers and boards, or for testing die sized components, such as unpackaged dice and chip scale packages.

摘要翻译： 用于测试半导体部件的测试系统包括具有基板和在基板上的触点的互连，用于电连接部件上的端子触点。 互连还包括在基板中形成靠近互连触点的柔性段的一个或多个空腔。 柔性部分允许互连触头在z方向上独立地移动以适应端子触头的高度和平面度的变化。 此外，空腔可以被加压，或交替地填充聚合物材料，以调节柔性段的符合性。 互连触点的不同实施例包括：用于保持端子触头的金属化凹槽，用于穿透端子触头的金属化突起，具有穿透突起的金属化凹槽以及包含在聚合物带上的引线，并悬挂在金属化凹槽上。 测试系统可以配置用于测试晶片尺寸的组件，如晶圆和电路板，或用于测试裸片大小的组件，如未封装的芯片和芯片级封装。

公开(公告)号：US07253957B2

公开(公告)日：2007-08-07

申请号：US10845303

申请日：2004-05-13

申请人： Salman Akram ,  Peter A. Benson

发明人： Salman Akram ,  Peter A. Benson

IPC分类号： G02B27/10 ,  H01L21/00

CPC分类号： G02B13/0085 ,  G02B3/0012 ,  G02B3/0056 ,  G02B7/02 ,  H01L27/14625 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02325 ,  H01L2224/48091 ,  H01L2924/15174 ,  H04N5/2253 ,  H04N5/2254 ,  H01L2924/00014

摘要： Microelectronic imagers, optical devices for microelectronic imagers, methods for manufacturing integrated optical devices for use with microelectronic imagers, and methods for packaging microelectronic imagers. The optical devices are manufactured in optical device assemblies that provide efficient and highly accurate fabrication of the optics that are used in microelectronic imagers. The optical device assemblies are particularly useful for packaging a plurality of microelectronic imagers at the wafer level. Wafer-level packaging is expected to significantly enhance the efficiency of manufacturing microelectronic imagers because a plurality of imagers can be packaged simultaneously using highly accurate and efficient processes developed for packaging processors, memory devices and other semiconductor devices.

摘要翻译： 微电子成像器，用于微电子成像器的光学器件，用于制造用于微电子成像器的集成光学器件的方法，以及用于封装微电子成像器的方法。 光学器件在光学器件组件中制造，其提供用于微电子成像器的光学器件的有效且高精度的制造。 光学器件组件特别适用于在晶片级封装多个微电子成像器。 预期晶圆级封装将显着提高制造微电子成像器的效率，因为可以使用为封装处理器，存储器件和其它半导体器件开发的高精度和有效的工艺来同时封装多个成像器。

公开(公告)号：US20070088451A1

公开(公告)日：2007-04-19

申请号：US11545067

申请日：2006-10-06

申请人： Salman Akram ,  Warren Farnworth ,  Derek Gouchnour ,  David Hembree ,  Michael Hess ,  John Jacobson ,  James Wark ,  Alan Wood

发明人： Salman Akram ,  Warren Farnworth ,  Derek Gouchnour ,  David Hembree ,  Michael Hess ,  John Jacobson ,  James Wark ,  Alan Wood

IPC分类号： G06F19/00

CPC分类号： G03F7/7065 ,  G06F11/006 ,  H01L2223/5444

摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the ICs. The ID codes of the ICs are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the ICs is then accessed, and additional repair procedures the ICs may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

摘要翻译： 在集成电路（IC）制造过程中的创造性方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修理，包括将数据与每个的熔丝ID相关联地存储 IC。 IC的ID代码在制造过程中例如在打开/短路测试中自动读取。 然后访问与IC的ID代码相关联存储的数据，并且根据所访问的数据选择IC可能经历的附加修复过程。 因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。