公开(公告)号：US20160086903A1

公开(公告)日：2016-03-24

申请号：US14672268

申请日：2015-03-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/15153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/03

Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The semiconductor structure includes a carrier, a semiconductor chip and an encapsulant. The semiconductor chip is disposed on the carrier, and has opposing non-active and active surfaces. The non-active surface is coupled to the carrier, and the active surface has a plurality of metallic pillars formed thereon. A under bump metallogy layer is formed between the metallic pillars and the active surface and on side surfaces of the metal pillars. The surface of the encapsulant is flush with end surfaces of the metallic pillars. Therefore, the product yield is increased significantly.

Abstract translation: 本发明提供一种半导体结构及其制造方法。 半导体结构包括载体，半导体芯片和密封剂。 半导体芯片设置在载体上，并且具有相对的非活性和有效表面。 非活性表面耦合到载体，并且活性表面上形成有多个金属柱。 在金属柱和活性表面之间以及金属柱的侧表面上形成凸块下金属层。 密封剂的表面与金属柱的端面齐平。 因此，产品产量明显增加。

公开(公告)号：US20160049359A1

公开(公告)日：2016-02-18

申请号：US14744289

申请日：2015-06-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: An interposer is provided, including a substrate body, a plurality of conductive posts formed in the substrate body, and a plurality of conductive pads formed on the substrate body and electrically connected to the conductive posts. The conductive pads and the conductive posts are integrally formed. As such, no interface is formed between the conductive pads and the conductive posts, thereby preventing delamination or cracking from occurring between the conductive pads and the conductive posts.

Abstract translation: 提供了一种插入器，包括基板主体，形成在基板主体中的多个导电柱，以及形成在基板主体上并电连接到导电柱的多个导电焊盘。 导电焊盘和导电柱一体形成。 因此，在导电焊盘和导电柱之间没有形成界面，从而防止在导电焊盘和导电柱之间发生分层或破裂。

公开(公告)号：US09875949B2

公开(公告)日：2018-01-23

申请号：US14981521

申请日：2015-12-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsiao-Chun Huang ,  Hsien-Wen Chen ,  Shih-Ching Chen ,  Guang-Hwa Ma

IPC: H01L23/12 ,  H01L21/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second sides; at least an electronic element disposed on the first side of the circuit structure; an encapsulant formed on the first side of the circuit structure for encapsulating the electronic element; a dielectric layer formed on portions of the second side of the circuit structure; and a metal structure formed on the dielectric layer and the circuit structure. The metal structure has a first metal layer bonded to the circuit structure and a second metal layer formed on the first metal layer and the dielectric layer. Therefore, by replacing a conventional silicon interposer with the circuit structure, the invention eliminates the need to fabricate through silicon vias so as to greatly reduce the fabrication difficulty and cost. The invention further provides a method for fabricating the electronic package.

公开(公告)号：US09502335B2

公开(公告)日：2016-11-22

申请号：US14487548

申请日：2014-09-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Hsien-Wen Chen ,  Hong-Da Chang ,  Mao-Hua Yeh

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/49 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15323 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.

Abstract translation: 提供一种封装结构，其包括：具有多个导电连接部分的芯片载体; 至少设置在所述芯片载体上的电子元件; 多个导线分别竖立设置在导电连接部分上; 形成在所述芯片载体上用于封装所述导线和所述电子元件的密封剂，其中所述导线的一端从所述密封剂露出; 以及形成在密封剂上并电连接到导线的露出端的电路层。 根据本发明，导线用作互连结构。 由于导线的线径小，导线之间的间距可以最小化，因此本发明可以减小芯片载体的尺寸并满足小型化要求。

公开(公告)号：US20160329267A1

公开(公告)日：2016-11-10

申请号：US14981521

申请日：2015-12-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsiao-Chun Huang ,  Hsien-Wen Chen ,  Shih-Ching Chen ,  Guang-Hwa Ma

IPC: H01L23/48 ,  H01L23/29 ,  H01L21/768 ,  H01L23/532 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/528

CPC classification number: H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second sides; at least an electronic element disposed on the first side of the circuit structure; an encapsulant formed on the first side of the circuit structure for encapsulating the electronic element; a dielectric layer formed on portions of the second side of the circuit structure; and a metal structure formed on the dielectric layer and the circuit structure. The metal structure has a first metal layer bonded to the circuit structure and a second metal layer formed on the first metal layer and the dielectric layer. Therefore, by replacing a conventional silicon interposer with the circuit structure, the invention eliminates the need to fabricate through silicon vias so as to greatly reduce the fabrication difficulty and cost. The invention further provides a method for fabricating the electronic package.

Abstract translation: 提供电子封装，其包括：具有相对的第一和第二侧的电路结构; 至少设置在电路结构的第一侧上的电子元件; 形成在用于封装电子元件的电路结构的第一侧上的密封剂; 形成在电路结构的第二侧的部分上的电介质层; 以及形成在电介质层和电路结构上的金属结构。 金属结构具有接合到电路结构的第一金属层和形成在第一金属层和介电层上的第二金属层。 因此，通过用电路结构代替传统的硅插入器，本发明消除了通过硅通孔制造的需要，从而大大降低了制造难度和成本。 本发明还提供一种制造电子封装的方法。

公开(公告)号：US20160307833A1

公开(公告)日：2016-10-20

申请号：US14981588

申请日：2015-12-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hsien-Wen Chen ,  Shih-Ching Chen ,  Hsiao-Chun Huang ,  Guang-Hwa Ma

IPC: H01L23/498 ,  H01L21/78 ,  H01L21/683 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic packaging structure is provided, including a circuit portion, an electronic element disposed on an upper side of the circuit portion and a glass carrier disposed on a lower side of the circuit portion. By replacing a conventional silicon wafer with the glass carrier, the present invention eliminates the need of an adhesive layer and allows quick removal of the glass carrier during a subsequent process, thus saving the fabrication time and increasing the product yield. The present invention further provides a method for fabricating an electronic package.

Abstract translation: 提供一种电子封装结构，包括电路部分，设置在电路部分上侧的电子元件和设置在电路部分下侧的玻璃载体。 通过用玻璃载体代替传统的硅晶片，本发明消除了对粘合剂层的需要，并允许在随后的工艺中快速去除玻璃载体，从而节省制造时间并提高产品产量。 本发明还提供一种电子封装的制造方法。

公开(公告)号：US20160148873A1

公开(公告)日：2016-05-26

申请号：US14833586

申请日：2015-08-24

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Hsien-Wen Chen ,  Kuang-Hsin Chen ,  Chung-Chih Yen ,  Wei-Jen Chang

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L23/147 ,  H01L23/15 ,  H01L23/5389 ,  H01L24/00 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/37001

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing a substrate having a cavity and a first via hole; disposing an electronic element in the cavity; forming a dielectric layer on the substrate and the electronic element; forming a circuit layer on the dielectric layer and forming a first conductive portion in the first via hole; forming on the substrate a second via hole communicating with the first via hole, the first and second via holes constituting a through hole; and forming a second conductive portion in the second via hole, the first and second conductive portions constituting a conductor. Since the through hole is formed through a two-step process, the invention can reduce the depth of the via holes and therefore perform laser drilling or etching processes with reduced energy, thereby avoiding damage of the conductive portions and improving the product reliability.

Abstract translation: 提供一种制造电子封装的方法，其包括以下步骤：提供具有空腔和第一通孔的基板; 将电子元件放置在空腔中; 在所述基板和所述电子元件上形成介电层; 在所述电介质层上形成电路层，并在所述第一通孔中形成第一导电部分; 在所述基板上形成与所述第一通孔连通的第二通孔，所述第一通孔和第二通孔构成通孔; 以及在所述第二通孔中形成第二导电部分，所述第一和第二导电部分构成导体。 由于通孔是通过两步法形成的，所以本发明可以减小通孔的深度，从而能够以较低的能量进行激光打孔或蚀刻处理，从而避免导电部的损坏，提高产品的可靠性。

公开(公告)号：US20160133556A1

公开(公告)日：2016-05-12

申请号：US14919867

申请日：2015-10-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Cheng-Hao Ciou ,  Cheng-Chieh Wu ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/29

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

Abstract translation: 提供了一种半导体封装，包括：绝缘基体，具有带有开口的第一表面和与第一表面相对的第二表面; 绝缘延伸体，其从所述绝缘基体的所述第一表面的边缘向外延伸，其中所述绝缘延伸体的厚度小于所述绝缘基体的厚度; 电子元件具有相对的有源和非活性表面并且设置在开口中，其非活性表面面向绝缘基体; 形成在所述绝缘基体的开口部和所述绝缘基体的所述第一面上的电介质层，所述绝缘延伸体和所述电子元件的有源面; 以及形成在电介质层上并电连接到电子元件的电路层。 本发明的绝缘层的结构有助于提高封装的整体结构刚度。

公开(公告)号：US09058971B2

公开(公告)日：2015-06-16

申请号：US13905703

申请日：2013-05-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Yuan Shih ,  Shih-Liang Peng ,  Jung-Pin Huang ,  Chin-Yu Ku ,  Hsien-Wen Chen

IPC: H01L27/15 ,  H01L29/26 ,  H01L31/12 ,  H01L33/00 ,  H01L25/00 ,  H01S5/022 ,  H01S5/024 ,  H01S5/062 ,  H01S5/42

CPC classification number: H01L25/00 ,  H01L2224/48091 ,  H01S5/02252 ,  H01S5/0226 ,  H01S5/02276 ,  H01S5/02288 ,  H01S5/02469 ,  H01S5/06226 ,  H01S5/423 ,  H01L2924/00014

Abstract: An electro-optical module is provided, which includes: a substrate having a first surface with a groove and an opposite second surface; a plurality of support members disposed on the first surface of the substrate; at least an electro-optical element having opposite active and non-active surfaces and disposed in the groove of the substrate via the non-active surface thereof; an interposer disposed on the first surface of the substrate and the electro-optical element for electrically connecting the electro-optical element to the substrate, wherein the interposer has a through hole corresponding in position to the active surface of the electro-optical element; and a transparent plate disposed over the first surface of the substrate and the interposer through the support members and having a lens portion corresponding in position to the through hole of the interposer, thereby reducing signal losses, improving alignment precision, and achieving preferred thermal dissipation and EMI shielding effects.

Abstract translation: 提供了一种电光模块，其包括：具有第一表面和第二表面的基板; 设置在所述基板的第一表面上的多个支撑构件; 至少一个电光元件具有相对的有源和非有源表面，并经由其非有效表面设置在衬底的沟槽中; 设置在基板的第一表面上的插入器和用于将电光元件电连接到基板的电光元件，其中插入器具有与电光元件的有源表面相对应的通孔; 以及设置在基板的第一表面上的透明板和穿过支撑构件的中介层，并且具有与插入件的通孔对应的透镜部分，从而减少信号损失，提高对准精度，并实现优选的散热和 EMI屏蔽效果。

公开(公告)号：US20140192832A1

公开(公告)日：2014-07-10

申请号：US13905703

申请日：2013-05-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Yuan Shih ,  Shih-Liang Peng ,  Jung-Pin Huang ,  Chin-Yu Ku ,  Hsien-Wen Chen

IPC: H01S5/062

CPC classification number: H01L25/00 ,  H01L2224/48091 ,  H01S5/02252 ,  H01S5/0226 ,  H01S5/02276 ,  H01S5/02288 ,  H01S5/02469 ,  H01S5/06226 ,  H01S5/423 ,  H01L2924/00014

Abstract: An electro-optical module is provided, which includes: a substrate having a first surface with a groove and an opposite second surface; a plurality of support members disposed on the first surface of the substrate; at least an electro-optical element having opposite active and non-active surfaces and disposed in the groove of the substrate via the non-active surface thereof; an interposer disposed on the first surface of the substrate and the electro-optical element for electrically connecting the electro-optical element to the substrate, wherein the interposer has a through hole corresponding in position to the active surface of the electro-optical element; and a transparent plate disposed over the first surface of the substrate and the interposer through the support members and having a lens portion corresponding in position to the through hole of the interposer, thereby reducing signal losses, improving alignment precision, and achieving preferred thermal dissipation and EMI shielding effects.

Abstract translation: 提供了一种电光模块，其包括：具有第一表面和第二表面的基板; 设置在所述基板的第一表面上的多个支撑构件; 至少一个电光元件具有相对的有源和非有源表面，并经由其非有效表面设置在衬底的沟槽中; 设置在基板的第一表面上的插入器和用于将电光元件电连接到基板的电光元件，其中插入器具有与电光元件的有源表面相对应的通孔; 以及设置在基板的第一表面上的透明板和穿过支撑构件的中介层，并且具有与插入件的通孔对应的透镜部分，从而减少信号损失，提高对准精度，并实现优选的散热和 EMI屏蔽效果。