公开(公告)号：US20170033037A1

公开(公告)日：2017-02-02

申请号：US15293883

申请日：2016-10-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Ching Ho ,  Ying-Chou Tsai ,  Sheng-Che Huang

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/81193 ,  H05K3/064 ,  H05K3/205 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4682 ,  H05K2201/0376 ,  Y02P70/613 ,  Y10T29/49158

Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

Abstract translation: 公开了一种封装基板，包括：介电层; 电介质层，其中所述电路层嵌入并暴露于所述电介质层的表面，其中所述电路层具有多个导电焊盘; 以及形成在所述导电焊盘上并突出在所述电介质层的表面上方的多个导电凸块。 这样，当通过多个导电元件将电子元件设置在导电焊盘上时，导电元件可以与导电凸块的顶表面和侧表面接触，从而增加导电元件与导电元件之间的接触面积 导电焊盘，从而加强导电元件和导电焊盘之间的接合，并防止导电元件与导电焊盘分层。

公开(公告)号：US09006039B2

公开(公告)日：2015-04-14

申请号：US14322372

申请日：2014-07-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Ching Ho ,  Yu-Chih Yu ,  Ying-Chou Tsai

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/48 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/83 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.

Abstract translation: 一种封装衬底的制造方法，包括：提供具有第一表面和与第一表面相对的第二表面的金属板，其中第一表面具有多个用于在其间限定第一芯电路层的第一开口，第二表面具有 用于在其间限定第二芯电路层的多个第二开口，所述第一开口和所述第二开口中的每一个具有宽的外部部分和窄的内部部分，并且每个所述第二开口的内部部分与所述第二开口的内部部分连通 第一开口中的对应的一个; 在第一开口中形成第一密封剂; 在所述第二开口中形成第二密封剂; 以及在第一密封剂和第一核心电路层上形成表面电路层。

公开(公告)号：US20150091150A1

公开(公告)日：2015-04-02

申请号：US14290145

申请日：2014-05-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Pang-Chun Lin ,  Wei-Ping Wang ,  Chun-Yuan Li ,  Shao-tzu Tang ,  Ying-Chou Tsai

IPC: H01L25/11 ,  H01L25/00

CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield.

Abstract translation: 公开了一种用于制造POP结构的方法。 首先，提供第一封装，其具有：介电层; 嵌入介电层中并从电介质层的上表面和下表面露出的堆叠电路层; 多个导电柱和设置在电介质层的上表面上并电连接到堆叠电路层的半导体芯片; 以及密封剂，其形成在所述电介质层的上表面上，用于封装所述半导体芯片和所述导电柱，并具有用于暴露所述导电柱的顶端的多个开口。 然后，第二包装被设置在密封剂上并电连接到导电柱。 导电柱的形成有助于减小密封剂的开口的深度，从而减少制造时间并提高生产效率和产率。

公开(公告)号：US20140091462A1

公开(公告)日：2014-04-03

申请号：US13729963

申请日：2012-12-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chia-Cheng Chen ,  Chi-Ching Ho ,  Shao-Tzu Tang ,  Yu-Che Liu ,  Ying-Chou Tsai

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2224/13099 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

Abstract translation: 提供一种半导体封装，其包括：由用于制造积层层结构的材料制成的电介质层; 形成在电介质层上的导电迹线层; 半导体芯片安装在导电迹线层上并电连接到导电迹线层上; 以及形成在电介质层上以封装半导体芯片和导电迹线层的密封剂。 由于在电介质层和导电迹线层之间形成牢固的接合，因此本发明能够防止电介质层与导电迹线层之间的分层发生，从而提高可靠性，并且通过现有的制造方法便于封装小型化。

公开(公告)号：US20200235462A1

公开(公告)日：2020-07-23

申请号：US16535022

申请日：2019-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Jung Tsai ,  Mao-Hua Yeh ,  Chih-Hsien Chiu ,  Ying-Chou Tsai ,  Chun-Chi Ke

IPC: H01Q1/22 ,  H01Q1/36 ,  H01L23/31 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.

公开(公告)号：US10201090B2

公开(公告)日：2019-02-05

申请号：US15615158

申请日：2017-06-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Ying-Chou Tsai

IPC: H05K1/00 ,  H05K3/00 ,  H05K1/11

Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.

公开(公告)号：US20180342446A1

公开(公告)日：2018-11-29

申请号：US15720552

申请日：2017-09-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Jia-Fong Yeh ,  Yi-Hsuan Liu ,  Mei-Chi Chen ,  Ying-Chou Tsai

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00

Abstract: A package structure and a method for fabricating the same are provided. An electronic component such as a sensing chip and a conductive element such as a bonding wire are mounted to a carrier, encapsulated by an encapsulant, and electrically connected through a conductive layer. As such, the electronic component can further be electrically connected to the carrier through the conductive layer and the conductive element. Therefore, the sensing chip can be packaged through current packaging processes, thereby reducing the fabrication cost, shortening the fabrication time and improving the product yield.

公开(公告)号：US09978673B2

公开(公告)日：2018-05-22

申请号：US15397927

申请日：2017-01-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Jia-Fong Yeh ,  Chien-Hui Wang ,  Chung-Yan Huang ,  Ying-Chou Tsai

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/60 ,  H01L23/00 ,  G06K9/00

CPC classification number: H01L23/49811 ,  G06K9/0002 ,  G06K9/00053 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/49805 ,  H01L23/562 ,  H01L23/60 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00014

Abstract: A package structure is provided, including a carrier, an electronic component disposed on the carrier and having a sensing area, an encapsulant formed on the carrier and encapsulating the electronic component and the sensing area, and a conductive layer formed on the encapsulant with the sensing area of the electronic component free from being covered by the conductive layer. The encapsulant prevents a user's finger from being in direct contact with the sensing area so as to protect the sensing area from being damaged and hence ensure normal operation of the electronic component.

公开(公告)号：US20160133593A1

公开(公告)日：2016-05-12

申请号：US14624642

申请日：2015-02-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Chang-Yi Lan ,  Ying-Chou Tsai

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/568 ,  H01L22/12 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00015 ,  H01L2924/1816 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/20 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/81

Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element;and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.

Abstract translation: 提供一种电子封装，其包括：具有多个电极焊盘的活性表面的电子元件，与该有源表面相对的非活性表面以及与该活性表面和非活性表面相邻并连接的侧表面; 形成在电子元件的电极焊盘上的多个导电元件; 以及覆盖电子元件的有源和侧表面以及导电元件的侧表面的部分并且暴露电子元件的非活性表面的密封剂。 因此，本发明提高了电子元件的有效表面的结构强度，以防止电子元件的破裂，从而避免导电元件与电子元件分层。

公开(公告)号：US09265154B2

公开(公告)日：2016-02-16

申请号：US14461828

申请日：2014-08-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Chi-Ching Ho ,  Ying-Chou Tsai

IPC: H01L21/8242 ,  H05K1/18 ,  H05K1/11 ,  H05K3/10 ,  H01L49/02

CPC classification number: H05K1/186 ,  H01L23/49822 ,  H01L23/50 ,  H01L28/40 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/10 ,  H05K3/42 ,  H05K2201/10015 ,  H05K2203/0733 ,  H01L2924/00

Abstract: A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.

Abstract translation: 提供一种封装基板的制造方法，其包括以下步骤：在载体上形成第一导电部分; 在每个第一导电部分上依次形成导电柱和取向层; 在载体上形成密封剂，用于封装第一导电部分，导电柱和对准层; 在所述密封剂中的每个取向层上形成导电孔，并在所述导电通孔和所述密封剂上形成第二导电部分; 并移除载体。 每个第一导电部分和相应的导电柱，对准层和导电通孔形成导电结构。 取向层具有大于导电柱和导电通孔的垂直投影面积，从而减小导电柱和导电通孔的尺寸，从而增加布线密度和电子元件安装密度。