公开(公告)号：US08970037B2

公开(公告)日：2015-03-03

申请号：US13960291

申请日：2013-08-06

Applicant: TDK Corporation

Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/485 ,  H01L23/492 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05571 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on the electrode; and a dome-shaped bump containing Sn and Ti, covering the under bump metal layer, wherein at least part of the under bump metal layer has a portion sandwiched between the external electrode and the insulating covering layer.

Abstract translation: 优选的端子结构包括基材; 形成在基材上的电极; 绝缘覆盖层，形成在所述基底材料上和所述电极上，并且具有暴露所述电极的至少一部分的开口; 含有Ni的下凸块金属层，填充电极上的开口; 以及包含Sn和Ti的圆顶状凸起，覆盖下凸块状金属层，其中至少部分下凸块金属层具有夹在外部电极和绝缘覆盖层之间的部分。

公开(公告)号：US11869834B2

公开(公告)日：2024-01-09

申请号：US17314187

申请日：2021-05-07

Applicant: TDK CORPORATION

Inventor： Takashi Daitoku ,  Susumu Taniguchi ,  Akiko Seki ,  Atsushi Sato ,  Yuhei Horikawa ,  Makoto Orikasa ,  Hisayuki Abe

IPC: H01L23/498 ,  H01L33/62 ,  H05K1/09 ,  H01L21/48 ,  H05K3/40 ,  G06F3/044

CPC classification number: H01L23/49838 ,  G06F3/044 ,  H01L21/4857 ,  H01L23/49866 ,  H01L33/62 ,  H05K1/09 ,  H05K3/4007 ,  H01L2933/0066 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2203/04

Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.

公开(公告)号：US11668008B2

公开(公告)日：2023-06-06

申请号：US17111040

申请日：2020-12-03

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Yuhei Horikawa ,  Yoshihiro Kanbayashi ,  Hisayuki Abe

IPC: B32B27/08 ,  B32B27/36 ,  B32B15/09 ,  B32B15/20 ,  B32B3/30 ,  H01L23/52 ,  H01L27/15 ,  B32B27/18 ,  H01L23/498 ,  H01L33/62 ,  H01L23/14 ,  H01L25/075 ,  C23C18/16 ,  C23C18/32 ,  C23C18/38 ,  C23C18/30 ,  C23F1/02

CPC classification number: C23C18/1641 ,  B32B3/30 ,  B32B15/09 ,  B32B15/20 ,  B32B27/08 ,  B32B27/18 ,  B32B27/36 ,  C23C18/161 ,  C23C18/1608 ,  C23C18/1651 ,  C23C18/30 ,  C23C18/32 ,  C23C18/38 ,  H01L23/52 ,  H01L27/156 ,  B32B2307/412 ,  B32B2457/20 ,  C23F1/02 ,  H01L23/145 ,  H01L23/498 ,  H01L25/0753 ,  H01L33/62

Abstract: A sheet material includes a resin layer containing a binder and catalyst particles, an electroless plating film on the side of one main surface of the resin layer and including first electroless plating films and a second electroless plating film, and a base material on the side of the other main surface of the resin layer.

公开(公告)号：US10392704B2

公开(公告)日：2019-08-27

申请号：US15415493

申请日：2017-01-25

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Yuhei Horikawa ,  Atsushi Sato ,  Hisayuki Abe

IPC: C23C18/42 ,  C23C18/16 ,  C23C18/32 ,  C23C18/54 ,  C23C28/02 ,  H01L23/00

Abstract: A method of providing a coating on a conductor. The coating has a first layer containing palladium and a second layer containing gold from the conductor side. The first layer has an inner layer on the conductor side and an outer layer arranged nearer to the second layer than the inner layer, and the outer layer has a higher phosphorus concentration than the inner layer.

公开(公告)号：US10362686B2

公开(公告)日：2019-07-23

申请号：US14862607

申请日：2015-09-23

Applicant: TDK CORPORATION

Inventor： Tsutomu Yasui ,  Hisayuki Abe ,  Kenichi Kawabata ,  Tomoko Kitamura

IPC: C22C19/03 ,  C22C13/00 ,  B23K35/30 ,  B23K35/26 ,  B23K35/02 ,  B32B15/01 ,  H05K3/34

Abstract: First solder is lead-free solder that contains no lead (Pb). The first solder includes a first metal that contains at least Sn; and a second metal that contains at least a Ni—Fe alloy.

公开(公告)号：US10354973B2

公开(公告)日：2019-07-16

申请号：US16037537

申请日：2018-07-17

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.

公开(公告)号：US10163847B2

公开(公告)日：2018-12-25

申请号：US15449361

申请日：2017-03-03

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.

公开(公告)号：US20180175494A1

公开(公告)日：2018-06-21

申请号：US15840192

申请日：2017-12-13

Applicant: TDK Corporation

Inventor： Yuhei Horikawa ,  Makoto Orikasa ,  Yoshihiro Kanbayashi ,  Hisayuki Abe ,  Hirohumi Asou ,  Kosuke Kunitsuka

IPC: H01Q1/38 ,  H01Q1/22 ,  H01Q7/00

CPC classification number: H01Q1/38 ,  H01Q1/2208 ,  H01Q1/2225 ,  H01Q7/00 ,  H04B5/0031 ,  H04B5/0081

Abstract: Disclosed herein is a wiring component that includes a base material and a planar coil pattern formed on the base material. The planar coil pattern includes a coil wiring portion having one end, other end, and first to third connecting positions, the second connecting position being closer to the other end compared with the first connecting position, the third connecting position being closer to the one end compared with the second connecting position; a power-feed wiring portion connected to the first connecting position; and a connection wiring portion that short-circuits the second connecting position and the third connecting position. A cross-section structure of the planar coil pattern has a base resin layer formed on the base material, and a conductive layer formed on the base resin layer.

公开(公告)号：US09818736B1

公开(公告)日：2017-11-14

申请号：US15449074

申请日：2017-03-03

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13611 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: A method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a smooth surface formation process of forming a smooth surface on the microbump, a lamination process of laminating three or more of the semiconductor chips by overlaying the microbump of one of the semiconductor chips on the microbump of another one of the semiconductor chips, and a bonding process of bonding the semiconductor chips to each other via the microbumps by heating to melt the microbumps, in which in the lamination process, of one of the semiconductor chips and another one of the semiconductor chips, the smooth surface is formed on at least one of the microbump, and one of the microbump contacts another one of the microbump on the smooth surface.

公开(公告)号：US09640500B2

公开(公告)日：2017-05-02

申请号：US13960173

申请日：2013-08-06

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: The present invention relates to a terminal structure comprising; a base material 10; an external electrode 20 formed on the base material; an insulating coating layer 30 formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layer 70 filling the opening and covering part of the insulating coating layer; and a dome-shaped bump 85 covering the under-bump metal layer, wherein in a cross section along a lamination direction, the under-bump metal layer has a convex shape toward the bump, and the thickness Tu0 of the under-bump metal layer at a center of the opening is equal to or greater than the thickness Tu1 of the under-bump metal layer at an end portion of the opening.