公开(公告)号：US20240178125A1

公开(公告)日：2024-05-30

申请号：US18071164

申请日：2022-11-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Masamitsu Matsuura

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49861 ,  H01L21/4803 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L21/561 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/29006 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83395 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83464 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/85395 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/85464 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01404 ,  H01L2924/0665

Abstract: In a described example, an apparatus includes: a metal leadframe including a dielectric die support formed in a central portion of the leadframe, and having metal leads extending from the central portion, portions of the metal leads extending into the central portion contacted by the dielectric die support; die attach material over the dielectric die support; a semiconductor die mounted to the dielectric die support by the die attach material, the semiconductor die having bond pads on a device side surface facing away from the dielectric die support; electrical connections extending from the bond pads to metal leads of the leadframe; and mold compound covering the semiconductor die, the electrical connections, the dielectric die support, and portions of the metal leads, the mold compound forming a package body.

公开(公告)号：US11736085B2

公开(公告)日：2023-08-22

申请号：US17002357

申请日：2020-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya Poddar ,  Hau Nguyen ,  Masamitsu Matsuura

IPC: H03H9/02 ,  H03H9/05 ,  H03H9/10 ,  H03H9/17 ,  H03H9/24 ,  H03H3/007 ,  H03H3/04

CPC classification number: H03H9/02133 ,  H03H3/0073 ,  H03H3/04 ,  H03H9/02102 ,  H03H9/02448 ,  H03H9/0523 ,  H03H9/0533 ,  H03H9/0547 ,  H03H9/1021 ,  H03H9/1057 ,  H03H9/17 ,  H03H9/2426 ,  H03H9/2457 ,  H03H2003/0407

Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.

公开(公告)号：US11410875B2

公开(公告)日：2022-08-09

申请号：US16225875

申请日：2018-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hau Thanh Nguyen ,  Woochan Kim ,  Yi Yan ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Masamitsu Matsuura ,  Kengo Aoya ,  Mutsumi Masumoto

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00

Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).

公开(公告)号：US11183441B2

公开(公告)日：2021-11-23

申请号：US16808018

申请日：2020-03-03

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

公开(公告)号：US20190385924A1

公开(公告)日：2019-12-19

申请号：US16008119

申请日：2018-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00

Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

公开(公告)号：US20160240392A1

公开(公告)日：2016-08-18

申请号：US15137114

申请日：2016-04-25

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mark Allen Gerber ,  Mutsumi Masumoto ,  Masamitsu Matsuura ,  Kengo Aoya ,  Takeshi Onogami

IPC: H01L21/56 ,  H01L21/48

CPC classification number: H01L21/561 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.

公开(公告)号：US20250074765A1

公开(公告)日：2025-03-06

申请号：US18456585

申请日：2023-08-28

Applicant: Texas Instruments Incorporated

Inventor： Daiki Komatsu ,  Masamitsu Matsuura ,  Mao Sugeno

IPC: B81B7/00 ,  B81C1/00

Abstract: An electronic device includes first and second semiconductor dies, the first semiconductor die having: a side extending in a first plane of orthogonal first and second directions; a sensor circuit along the side; and a conductive terminal extending outward from the side along an orthogonal third direction, and the second semiconductor die bonded to the first semiconductor die and having: a bottom side; a lateral side; and an insulation layer, the bottom side spaced apart from and facing the side of the first semiconductor die to form a protected chamber for the sensor circuit, the lateral side of the second semiconductor die spaced apart from the conductive terminal along the first direction, the insulation layer extending along the lateral side of the second semiconductor die, and the insulation layer spaced apart from and facing the conductive terminal along the first direction.

公开(公告)号：US20240421120A1

公开(公告)日：2024-12-19

申请号：US18816640

申请日：2024-08-27

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mahmud Chowdhury ,  Hau Nguyen ,  Masamitsu Matsuura ,  Ting-Ta Yen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes forming a stress sensitive component on a first semiconductor die; forming a solder seal on the first semiconductor die, the solder seal extending from a first surface of the first semiconductor die, and surrounding the stress sensitive component, the solder seal having an interior surface that surrounds the stress sensitive component and having an exterior surface facing away from the stress sensitive component; flip chip mounting the first semiconductor die to a first surface of a second semiconductor die, the stress sensitive component facing the first surface of the second semiconductor die; and forming a solder joint between the solder seal and the first surface of the second semiconductor die.

公开(公告)号：US12074134B2

公开(公告)日：2024-08-27

申请号：US17364769

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mahmud Chowdhury ,  Hau Nguyen ,  Masamitsu Matsuura ,  Ting-Ta Yen

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/94 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/16 ,  H01L25/0657 ,  H01L24/95 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2924/182

Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.

公开(公告)号：US12057417B2

公开(公告)日：2024-08-06

申请号：US16739578

申请日：2020-01-10

Applicant: Texas Instruments Incorporated

Inventor： Masamitsu Matsuura ,  Daiki Komatsu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/11013 ,  H01L2224/11334

Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.