摘要:
A nano-sized metal particle composite includes a first metal that has a particle size of about 50 nanometer or smaller. A wire interconnect is in contact with a reflowed nanosolder and has the same metal or alloy composition as the reflowed nanosolder. A microelectronic package is also disclosed that uses the reflowed nanosolder composition. A method of assembling a microelectronic package includes preparing a wire interconnect template. A computing system includes a nanosolder composition coupled to a wire interconnect.
摘要:
A nano-sized metal particle composite includes a first metal that has a particle size of about 50 nanometer or smaller. A wire interconnect is in contact with a reflowed nanosolder and has the same metal or alloy composition as the reflowed nanosolder. A microelectronic package is also disclosed that uses the reflowed nanosolder composition. A method of assembling a microelectronic package includes preparing a wire interconnect template. A computing system includes a nanosolder composition coupled to a wire interconnect.
摘要:
In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.
摘要:
Lead-free solders comprising 85-96% tin (Sn) and 4-15% Indium (In) by weight percentage (wt. %) and exemplary uses of the same are disclosed. The Sn—In solder undergoes a martensitic phase change when it is cooled from a reflow temperature to room temperature. As a result, residual stresses that would normally occur due to solder strain caused by relative movement between joined components are substantially reduced. Typically, the relative movement results from a coefficient of thermal expansion (CTE) mismatch between the joined components. The disclosed exemplary uses include flip-chip assembly and IC package to circuit board mounting, such as ball grid array packages.
摘要:
A system includes a thermal interface material (TIM) to transfer heat from a die to a heat spreader. The system includes a heat transfer subsystem disposed on the backside surface of the die. In one embodiment, the heat transfer subsystem comprises a first heat transfer material and a second heat transfer material discretely disposed within the first heat transfer material. A method of bonding a die to a heat spreader uses a die-referenced process as opposed to a substrate-referenced process.
摘要:
A polymer solder hybrid (PSH) thermal interface material (TIM). The PSH TIM includes a solder with a low melt temperature and a filler with a high melt temperature. Upon initiation of reflow, the filler diffuses into the solder to form a new filler-solder alloy having an increased melting point and added robustness.
摘要:
A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress.
摘要:
A composite of two or more thermal interface materials (“TIMs”) is placed between a die and a heat spreader to improve cooling of the die in an integrated circuit package. The two or more TIMs vary in heat-dissipation capability depending upon the locations of die hot spots. In an embodiment, a more thermally conductive material may be positioned over one or more die hot spots, and a less thermally conductive material may be positioned abutting and/or surrounding the more thermally conductive material. The two or more TIMs may comprise a solder and a polymer. The composite TIM may be preformed as one unit or as a plurality of units. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
摘要:
A microelectronic package is disclosed including a microelectronic device, a substrate, and a signaling path coupling the microelectronic device with the substrate. The signaling path includes a conductive material, a solder joint, and a barrier material disposed between the conductive material and the solder joint. The barrier material may include nickel, cobalt, iron, titanium, and combinations thereof.
摘要:
A structure including a substrate, a copper bump formed over the substrate, and a barrier layer comprising an alloy of at least one of iron and nickel, formed over the copper bump, and methods to make such a structure.