公开(公告)号：US11121031B2

公开(公告)日：2021-09-14

申请号：US16668570

申请日：2019-10-30

Applicant: XINTEC INC.

Inventor： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/02

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

公开(公告)号：US09640683B2

公开(公告)日：2017-05-02

申请号：US14640307

申请日：2015-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/0236 ,  H01L31/02 ,  H01L31/0203 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US09570398B2

公开(公告)日：2017-02-14

申请号：US13895219

申请日：2013-05-15

Applicant: XINTEC INC.

Inventor： Shu-Ming Chang ,  Yu-Ting Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/538 ,  H01L21/78 ,  H01L23/48 ,  B81B7/00 ,  H01L23/00 ,  H01L21/683 ,  H01L23/60

CPC classification number: H01L23/5384 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/481 ,  H01L23/60 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05617 ,  H01L2224/05624 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/10155 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2224/80 ,  H01L2224/83 ,  H01L21/304 ,  H01L21/76898 ,  H01L2221/68304 ,  H01L2224/0231 ,  H01L2224/11

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一基板; 设置在其上的第二基板，其中所述第二基板包括下半导体层，上半导体层和绝缘层，并且所述下半导体层的一部分与所述第一基板上的至少一个焊盘电接触; 导电层，其设置在所述第二基板的所述上半导体层上并电连接到所述下半导体层与所述至少一个焊盘电接触的部分; 从上半导体层向下半导体层延伸并延伸到下半导体层的开口; 以及设置在所述上​​半导体层和所述导电层上的保护层，其中所述保护层延伸到所述开口的侧壁的一部分上，并且不覆盖所述开口中的下半导体层。

公开(公告)号：US09214579B2

公开(公告)日：2015-12-15

申请号：US14534684

申请日：2014-11-06

Applicant: XINTEC INC.

Inventor： Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/0232 ,  H01L31/02 ,  H01L31/18 ,  H01L31/0236

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了具有硅衬底和保护层的晶片结构。 保护层上的电焊盘通过硅衬底的凹入区露出。 在硅基板的侧壁上形成隔离层，该隔离层包围该凹陷区域以及该硅基板的远离该保护层的表面。 在隔离层和电焊盘上形成再分布层。 在再分布层上形成钝化层。 图案化钝化层以在其中形成第一开口。 在通过第一开口露出的再分布层上形成第一导电层。 导电结构布置在第一开口中，使得导电结构与第一导电层电接触。

公开(公告)号：US09177862B2

公开(公告)日：2015-11-03

申请号：US13727976

申请日：2012-12-27

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Hsin Kuan ,  Long-Sheng Yeou ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L21/56 ,  H01L23/498 ,  H01L21/78 ,  H01L23/48 ,  H01L23/28 ,  H01L21/82 ,  H01L23/14 ,  H01L21/683 ,  H01L21/768 ,  B81B7/00 ,  H01L23/00

CPC classification number: H01L21/82 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/14 ,  H01L23/147 ,  H01L24/08 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/80006 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/1461 ,  H01L2224/82 ,  H01L2224/80 ,  H01L21/78

Abstract: A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.

Abstract translation: 半导体堆叠结构的制造方法主要包括：将第一规格的晶片分割成多个芯片; 将芯片重新排列成晶片的第二规格，以通过多个块将芯片堆叠在第二规格的基板上; 在芯片上形成再分配层; 并执行切割处理以获得多个半导体堆叠结构。 因此，本发明允许通过使用常规设备来处理新规格的晶片，而不需要新的工厂建筑物或设备。 因此，可以及时提供芯片封装以满足电子产品的更换速度。

公开(公告)号：US09153707B2

公开(公告)日：2015-10-06

申请号：US13912792

申请日：2013-06-07

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Ying-Nan Wen ,  Tsang-Yu Liu

IPC: H01L31/0232 ,  H01L31/02 ,  H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/02002 ,  H01L31/0232 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 设置在所述半导体衬底中的器件区域; 设置在所述半导体衬底的第一表面上的电介质层; 布置在所述电介质层中并电连接到所述器件区的导电焊盘结构，设置在所述电介质层上的载体衬底; 以及设置在所述载体基板的底表面中并与所述导电焊盘结构电接触的导电结构。

公开(公告)号：US09054114B2

公开(公告)日：2015-06-09

申请号：US14290638

申请日：2014-05-29

Applicant: XINTEC INC.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Chen-Han Chiang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一实施例提供一种芯片封装结构。

公开(公告)号：US08975755B2

公开(公告)日：2015-03-10

申请号：US14171734

申请日：2014-02-03

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/481 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48151 ,  H01L2224/73207 ,  H01L2924/10156 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.

Abstract translation: 本公开的一个实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 电线层，其设置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中; 位于所述导线层和所述半导体基板之间的绝缘层; 设置在所述第一表面上的芯片; 以及设置在所述芯片和所述第一表面之间的导电结构。

公开(公告)号：US08951836B2

公开(公告)日：2015-02-10

申请号：US14214389

申请日：2014-03-14

Applicant: Xintec Inc.

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L21/44 ,  H01L21/768 ,  B81B7/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for forming a chip package, in which a substrate has a plurality of conducting pads located below its lower surface, and a dielectric layer located between the conducting pads. A hole is formed extending from the upper surface of the substrate towards the conducting pads. After the hole is formed, a trench is formed extending from the upper surface towards the lower surface of the substrate, with the trench connecting with the hole. An insulating layer is formed on a sidewall of the trench and a sidewall and a bottom of the hole, and a portion of the insulating layer and a portion of the dielectric layer are removed to expose a portion of the conducting pads. A conducting layer is formed on the sidewall of the trench and the sidewall and the bottom of the hole, electrically contacting with the conducting pads.

Abstract translation: 一种用于形成芯片封装的方法，其中衬底具有位于其下表面下方的多个导电焊盘以及位于导电焊盘之间的电介质层。 形成从衬底的上表面朝向导电垫延伸的孔。 在形成孔之后，形成从衬底的上表面向下表面延伸的沟槽，沟槽与孔连接。 绝缘层形成在沟槽的侧壁和孔的侧壁和底部上，绝缘层的一部分和电介质层的一部分被去除以暴露导电垫的一部分。 导电层形成在沟槽的侧壁和孔的侧壁和底部，与导电垫电接触。

公开(公告)号：US08900924B2

公开(公告)日：2014-12-02

申请号：US14173340

申请日：2014-02-05

Applicant: Xintec Inc.

Inventor： Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L25/00 ,  H01L21/822 ,  B81C1/00 ,  H01L21/768 ,  H01L23/10 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/10 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14517 ,  H01L2224/17517 ,  H01L2224/73103 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在第一芯片上的第二芯片; 从所述第一芯片的表面向所述第二芯片延伸的孔; 导电层，设置在所述第一芯片的表面上并延伸到所述孔中并电连接到所述第一芯片中的导电区域或掺杂区域; 以及设置在所述第一芯片和所述第二芯片之间的支撑体，其中所述支撑体基本上和/或完全覆盖所述孔的底部。