公开(公告)号：US06358832B1

公开(公告)日：2002-03-19

申请号：US09641834

申请日：2000-08-18

申请人： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

发明人： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76835

摘要： A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

摘要翻译： 包含双蚀刻停止/扩散屏障的镶嵌互连。 镶嵌互连的导电材料用导电金属扩散阻挡盖（通常使用无电沉积）和可选地与电介质蚀刻停止层封盖。 还可以存在任选的化学机械抛光 - 停止层。 本发明的不同方法允许不同层的CMP停止，反应离子蚀刻停止和金属扩散阻挡层要求被去耦合。 优选的导电材料是铜。

公开(公告)号：US06341418B1

公开(公告)日：2002-01-29

申请号：US09301890

申请日：1999-04-29

申请人： Guy P. Brouillette ,  David H. Danovitch ,  Peter A. Gruber ,  Michael Liehr ,  Carlos J. Sambucetti

发明人： Guy P. Brouillette ,  David H. Danovitch ,  Peter A. Gruber ,  Michael Liehr ,  Carlos J. Sambucetti

IPC分类号： H05K334

CPC分类号： H01L21/563 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  H01L2924/00

摘要： A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads. In the bonded assembly, the in-situ polymeric mold layer and the underfill material layer forms a composite underfill to replace a conventional underfill material that must be injected between bonded chip and substrate by a capillary action in a time consuming process.

摘要翻译： 公开了一种通过使用焊料凸块和底部填充层将半导体芯片直接贴合到电路板的方法。 在该方法中，首先在半导体芯片的顶表面上丝网印刷一层原位聚合物模材料，暴露出多个接合焊盘。 原位聚合物模具层形成有多个孔，然后在熔融焊料筛选过程中用焊料材料填充以形成焊料凸块。 然后将薄的含有焊剂的底层填充材料层放置在电路板的顶部上，该多个导电焊盘以镜像形式布置在半导体芯片上的接合焊盘上。 然后将半导体芯片和电路板与其中的底部填充层一起压在一起，并被加热到高于焊料材料的熔融温度的回流温度，直到在焊盘和导电焊盘之间建立电连通。 在粘合组件中，原位聚合物模层和底部填充材料层形成复合底层填料，以代替在耗时的过程中必须通过毛细管作用在粘合的芯片和衬底之间注入的常规底部填充材料。

公开(公告)号：US06339024B1

公开(公告)日：2002-01-15

申请号：US09605728

申请日：2000-06-28

申请人： Kevin S. Petrarca ,  John E. Heidenreich, III ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Richard P. Volant ,  George F. Walker

发明人： Kevin S. Petrarca ,  John E. Heidenreich, III ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L2044

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14

摘要： A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.

摘要翻译： 一种制造集成电路的方法，其中提供具有大于或等于1.5μm厚度的集成电路的最上半导体层中的导电结构。 导电结构的厚度足够大，以有效地保护最高半导体层下面的任何层免受来自压力（例如由测试探针施加的压力）的损害。 在优选的实施方案中，传统的铝TD匀染被丢弃，有利于沉积在增厚的导电层上的金。

公开(公告)号：US06335104B1

公开(公告)日：2002-01-01

申请号：US09510996

申请日：2000-02-22

申请人： Carlos J. Sambucetti ,  Daniel C. Edelstein ,  John G. Gaudiello ,  Judith M. Rubino ,  George Walker

发明人： Carlos J. Sambucetti ,  Daniel C. Edelstein ,  John G. Gaudiello ,  Judith M. Rubino ,  George Walker

IPC分类号： B32B1500

CPC分类号： H01L24/48 ,  C23C18/1608 ,  C23C18/1651 ,  C23C18/1831 ,  C23C18/1844 ,  C23C18/34 ,  C23C18/36 ,  C23C18/54 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48739 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48799 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48864 ,  H01L2224/48869 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H05K3/244 ,  H05K13/06 ,  Y10S428/926 ,  Y10S428/936 ,  Y10T428/12493 ,  Y10T428/12646 ,  Y10T428/12674 ,  Y10T428/12771 ,  Y10T428/12778 ,  Y10T428/12875 ,  Y10T428/12889 ,  Y10T428/12896 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/12944 ,  Y10T428/12986 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00015

摘要： A method for preparing a copper pad surface for electrical connection that has superior diffusion barrier and adhesion properties is provided. In the method, a copper pad surface is first provided that has been cleaned by an acid solution, a protection layer of a phosphorus or boron-containing metal alloy is then deposited on the copper pad surface, and then an adhesion layer of a noble metal is deposited on top of the protection layer. The protection layer may be a single layer, or two or more layers intimately joined together formed of a phosphorus or boron-containing metal alloy such as Ni-P, Co-P, Co-W-P, Co-Sn-P, Ni-W-P, Co-B, Ni-B, Co-Sn-B, Co-W-B and Ni-W-B to a thickness between about 1,000 Å and about 10,000 Å. The adhesion layer can be formed of a noble metal such as Au, Pt, Pd and Ag to a thickness between about 500 Å and about 4,000 Å.

摘要翻译： 提供了一种制备具有优异的扩散阻挡层和粘合性能的用于电连接的铜焊盘表面的方法。 在该方法中，首先提供已经被酸溶液清洗的铜焊盘表面，然后在铜焊盘表面上沉积磷或含硼金属合金的保护层，然后将贵金属的粘附层 沉积在保护层的顶部。 保护层可以是由磷或含硼金属合金如Ni-P，Co-P，Co-WP，Co-Sn-P，Ni-WP紧密连接在一起的两层或更多层 ，Co-B，Ni-B，Co-Sn-B，Co-WB和Ni-WB，厚度在约至Å至约Å之间。 粘合层可以由贵金属如Au，Pt，Pd和Ag形成，厚度在约至约4,000之间。

公开(公告)号：US5866044A

公开(公告)日：1999-02-02

申请号：US734492

申请日：1996-10-21

申请人： Ravi F. Saraf ,  Judith Marie Roldan ,  Michael Anthony Gaynes ,  Richard Benton Booth ,  Steven Paul Ostrander ,  Emanuel I. Cooper ,  Carlos J. Sambucetti

发明人： Ravi F. Saraf ,  Judith Marie Roldan ,  Michael Anthony Gaynes ,  Richard Benton Booth ,  Steven Paul Ostrander ,  Emanuel I. Cooper ,  Carlos J. Sambucetti

IPC分类号： H01B1/22 ,  H01L21/60 ,  H01L23/498 ,  H05K3/32 ,  H05K3/46 ,  H01B1/12

CPC分类号： H01L24/81 ,  H01B1/22 ,  H01L23/49883 ,  H05K3/321 ,  H01L2224/13009 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K2201/0129 ,  H05K2201/0133 ,  H05K2201/0162 ,  H05K2203/0783 ,  H05K3/4614 ,  H05K3/4632

摘要： An electrically conductive paste which includes a thermoplastic polymer, a conductive metal powder and an organic solvent system is disclosed. The invention further encompasses an electrically conductive composite which includes the aforementioned thermoplastic and metal, wherein the metal represents at least about 30% by volume, based on the total volume of the composite. The composite is formed from the paste under elevated temperature. The paste is employed in processes which involve electrically connecting electrical and electronic components under process conditions which convert the paste to the composite.

摘要翻译： 公开了一种包括热塑性聚合物，导电金属粉末和有机溶剂系统的导电浆料。 本发明还包括一种包含上述热塑性和金属的导电复合材料，其中基于复合材料的总体积，金属占体积的至少约30体积％。 复合材料由高温下的糊料形成。 该糊剂用于涉及将糊料转化为复合材料的工艺条件下的电气和电子部件电连接的工艺。

公开(公告)号：US5079070A

公开(公告)日：1992-01-07

申请号：US595902

申请日：1990-10-11

申请人： Pedro A. Chalco ,  Carlos J. Sambucetti

发明人： Pedro A. Chalco ,  Carlos J. Sambucetti

IPC分类号： B23K20/10 ,  B23K26/32 ,  G02F1/13 ,  H05K3/20 ,  H05K3/22 ,  H05K3/24 ,  H05K3/32 ,  H05K3/46

CPC分类号： H05K3/225 ,  B23K20/10 ,  G02F1/1309 ,  H05K2201/0317 ,  H05K2201/1028 ,  H05K2203/0278 ,  H05K2203/0285 ,  H05K2203/107 ,  H05K2203/173 ,  H05K3/20 ,  H05K3/244 ,  H05K3/328 ,  Y10S428/901 ,  Y10S428/913 ,  Y10T428/24917 ,  Y10T428/31678 ,  Y10T428/31721

摘要： Open defects in thin film conductor lines on a substrate are repaired by diffusion bonding a selected conductive repair line from a support sheet positioned over the open defect. The diffusion bonding is performed by the application of ultrasonic energy and laser energy.

摘要翻译： 通过将所选择的导电修复线从位于开放缺陷上的支撑片扩散接合来修复衬底上的薄膜导体线中的开放缺陷。 通过施加超声能量和激光能量来进行扩散接合。

公开(公告)号：US4478883A

公开(公告)日：1984-10-23

申请号：US398140

申请日：1982-07-14

申请人： James R. Bupp ,  Voya Markovich ,  Tracy E. Napp ,  Carlos J. Sambucetti

发明人： James R. Bupp ,  Voya Markovich ,  Tracy E. Napp ,  Carlos J. Sambucetti

IPC分类号： H05K3/18 ,  C23C18/18 ,  C23C18/20 ,  C23C18/30 ,  H05K3/38 ,  C23C3/02

CPC分类号： H05K3/381 ,  C23C18/1858 ,  C23C18/1865 ,  C23C18/1893

摘要： A dielectric surface is conditioned for electroless plating of a conductive metal thereon by contacting the surface with a multifunctional ionic copolymer. The conditioning can be in the holes and/or on the surfaces of the substrate.

摘要翻译： 通过使表面与多功能离子共聚物接触，对电介质表面进行调理，以使其上的导电金属化学镀。 调理可以在基底的孔和/或表面上。

公开(公告)号：US4448804A

公开(公告)日：1984-05-15

申请号：US540600

申请日：1983-10-11

申请人： William J. Amelio ,  Gary K. Lemon ,  Voya Markovich ,  Theodore Panasik ,  Carlos J. Sambucetti ,  Donna J. Trevitt

发明人： William J. Amelio ,  Gary K. Lemon ,  Voya Markovich ,  Theodore Panasik ,  Carlos J. Sambucetti ,  Donna J. Trevitt

IPC分类号： C23C18/16 ,  C23C18/40 ,  C23C18/52 ,  H05K3/18 ,  H05K3/38 ,  B05D5/12 ,  B05D1/32 ,  B05D3/04 ,  C23F1/00

CPC分类号： H05K3/381 ,  C23C18/1605 ,  C23C18/1651 ,  C23C18/1893 ,  C23C18/2086 ,  C23C18/285 ,  C23C18/30 ,  C23C18/405 ,  H05K3/181 ,  H05K2203/1407

摘要： Multistep process for electroless plating of copper onto a non-conductive surface including the steps of: (1) laminating a rough copper sheet onto the non-conductive surface; (2) etching away all the copper; (3) conditioning the surface with multifunctional positively charged molecules derived from copolymers of polyacrylamide and functionally active tetraalkylammonium compounds in an diluted inorganic acid; (4) activating the conditioned surface preferably with stannous/palladium chloride particles; (5) treating the activated surface with deionized water and diluted HCl; (6) applying a photoresist layer to the surface and selectively exposing and developing the photoresist to produce a mask corresponding to the negative of the desired circuit pattern; and (7) plating copper using successively two baths differing in their oxygen and CN.sup.- concentration, where the foregoing steps are interspersed with washing steps.

摘要翻译： 包括以下步骤：（1）将铜铜层压到非导电表面上; （2）蚀刻所有铜; （3）用稀释的无机酸中的聚丙烯酰胺和功能活性四烷基铵化合物的共聚物衍生的多官能带正电的分子调理表面; （4）优选用亚锡/氯化钯粒子活化调理表面; （5）用去离子水和稀HCl稀释活化表面; （6）将光致抗蚀剂层施加到表面并选择性地曝光和显影光致抗蚀剂以产生对应于所需电路图案的负片的掩模; 和（7）使用连续两个不同氧气和CN-浓度的浴电镀铜，其中上述步骤穿过洗涤步骤。