公开(公告)号：US09293409B2

公开(公告)日：2016-03-22

申请号：US14023493

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L21/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L21/784 ,  H01L23/482

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

Abstract translation: 根据各种实施例，半导体器件的制造方法可以包括提供半导体工件，其包括在半导体工件的第一侧的器件区域，其中半导体工件的机械稳定性不足以抵抗至少一个后端工艺，而没有 损坏，并且在半导体工件的与半导体工件的第一侧相对的第二侧上沉积至少一个导电层，其中至少一个导电层增加半导体工件的机械稳定性，以足以抵抗至少一个 后端程序无损坏。

公开(公告)号：US20150091183A1

公开(公告)日：2015-04-02

申请号：US14042750

申请日：2013-10-01

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn ,  Edward Fuergut

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing side of the die, and the die further including at least a third terminal on the second side; a first electrically conductive structure providing current flow from the third terminal on second side of the die to the first side through the die; a second electrically conductive structure on the first side of the die laterally coupling the second terminal with the first electrically conductive structure; and an encapsulation material disposed at least over the first side of the die covering the first terminal and the second electrically conductive structure.

Abstract translation: 提供了一种安排。 该装置可以包括：模具，其包括至少一个电子部件和在模具的第一侧上的第一端子，以及在模具的与第一侧相对的第二侧上的第二端子，其中第一侧是主要处理侧 所述管芯和所述管芯还包括在所述第二侧上的至少第三端子; 第一导电结构，其提供从模具的第二侧上的第三端子到通过模具的第一侧的电流; 在所述模具的第一侧上的第二导电结构将所述第二端子与所述第一导电结构横向地联接; 以及封装材料，其至少设置在覆盖所述第一端子和所述第二导电结构的所述管芯的所述第一侧的上方。

公开(公告)号：US11233493B2

公开(公告)日：2022-01-25

申请号：US15934387

申请日：2018-03-23

Applicant: Infineon Technologies AG

Inventor： Hans-Joerg Timme ,  Carsten Ahrens ,  Ruediger Bauder

IPC: H03H3/02 ,  H03H9/205 ,  H03H9/17 ,  H01L41/277 ,  H03H9/58 ,  H03H9/02

Abstract: Methods for manufacturing resonator structures and corresponding resonator structures are described. A first wafer including a first piezoelectric material is singulated and bonded to a second wafer.

公开(公告)号：US20180108622A1

公开(公告)日：2018-04-19

申请号：US15730466

申请日：2017-10-11

Applicant: Infineon Technologies AG

Inventor： Carsten Ahrens ,  Katharina Umminger ,  Carsten von Koblinski

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/64 ,  H01L25/11

CPC classification number: H01L23/66 ,  H01L21/6835 ,  H01L23/5222 ,  H01L23/645 ,  H01L25/112 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1423 ,  H01L2924/1431 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/03 ,  H01L2224/11

Abstract: In accordance with an embodiment, an RF module includes a bulk semiconductor substrate with at least one integrated RF component integrated in a first main surface region of the bulk semiconductor substrate; an insulator structure surrounding a side surface region of the bulk semiconductor substrate; a wiring layer stack including at least one structured metallization layer embedded into an insulation material, the wiring layer stack being arranged on the first main surface region of the bulk semiconductor substrate and a first main surface region of the insulator structure; and a carrier structure at a second main surface region of the insulator structure, wherein the carrier structure and the insulator structure include different materials.

公开(公告)号：US20170365507A1

公开(公告)日：2017-12-21

申请号：US15630597

申请日：2017-06-22

Applicant: Infineon Technologies AG

Inventor： Alfons Dehe ,  Damian Sojka ,  Andre Schmenn ,  Carsten Ahrens

IPC: H01L21/762 ,  H01L23/60 ,  H01L21/764 ,  H02H9/04 ,  H01L27/02 ,  H01L23/00

CPC classification number: H01L21/76289 ,  B81C1/00119 ,  B81C1/00214 ,  B81C1/00404 ,  B81C1/00484 ,  B81C1/00531 ,  B81C1/00539 ,  B81C1/00571 ,  B81C2201/0111 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0135 ,  B81C2201/016 ,  B81C2201/0198 ,  B81C2201/053 ,  H01J1/3044 ,  H01J1/308 ,  H01J2201/30411 ,  H01J2201/3048 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/283 ,  H01L21/31058 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/31144 ,  H01L21/764 ,  H01L23/60 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L27/0288 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H02H9/046 ,  H03K17/545 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device.

公开(公告)号：US20160372256A1

公开(公告)日：2016-12-22

申请号：US15256305

申请日：2016-09-02

Applicant: Infineon Technologies AG

Inventor： Gunther Mackh ,  Carsten Ahrens ,  Klemens Pruegl

IPC: H01F27/28 ,  H01F27/255 ,  H01L49/02 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F5/00 ,  H01F17/0006 ,  H01F17/04 ,  H01F27/255 ,  H01F41/046 ,  H01F2017/048 ,  H01L23/5227 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2924/00011 ,  H01L2924/01047 ,  H01L2924/30107 ,  H05K3/10 ,  Y10T29/49075 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01005

Abstract: In one embodiment, an inductor has a substrate, a conductor disposed above the substrate and a seamless ferromagnetic material surrounding at least a first portion of the conductor.

公开(公告)号：US20160318759A1

公开(公告)日：2016-11-03

申请号：US15206836

申请日：2016-07-11

Applicant: Infineon Technologies AG

Inventor： Alfons Dehe ,  Stephan Pindl ,  Bernhard Knott ,  Carsten Ahrens

IPC: B81C1/00 ,  H04R19/04 ,  H04R31/00 ,  H04R19/00

CPC classification number: B81C1/00825 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C1/00873 ,  B81C2201/017 ,  B81C2201/053 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00 ,  H04R2201/003

Abstract: A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack on a first main surface of a substrate, forming a polymer layer on a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.

Abstract translation: 公开了一种制造MEMS器件的方法。 此外，公开了一种MEMS器件和包括MEMS器件的模块。 一个实施例包括用于制造MEMS器件的方法，包括在衬底的第一主表面上形成MEMS堆叠，在衬底的第二主表面上形成聚合物层，并在聚合物层和衬底中形成第一开口，使得 第一个开口与MEMS堆栈相邻。

公开(公告)号：US09102519B2

公开(公告)日：2015-08-11

申请号：US13804934

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Alfons Dehe ,  Carsten Ahrens ,  Stefan Barzen ,  Wolfgang Friza

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0072 ,  B81B3/001 ,  B81B3/0027 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00182 ,  B81C1/00404 ,  B81C1/00984 ,  B81C2201/017 ,  B81C2201/115

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a sacrificial layer over a first surface of a workpiece having the first surface and an opposite second surface. A membrane is formed over the sacrificial layer. A through hole is etched through the workpiece from the second surface to expose a surface of the sacrificial layer. At least a portion of the sacrificial layer is removed from the second surface to form a cavity under the membrane. The cavity is aligned with the membrane.

Abstract translation: 根据本发明的实施例，形成半导体器件的方法包括在具有第一表面和相对的第二表面的工件的第一表面上形成牺牲层。 在牺牲层上形成膜。 从第二表面通过工件蚀刻通孔以暴露牺牲层的表面。 牺牲层的至少一部分从第二表面移除以在膜下形成空腔。 空腔与膜对准。

公开(公告)号：US08975612B2

公开(公告)日：2015-03-10

申请号：US14219944

申请日：2014-03-19

Applicant: Infineon Technologies AG

Inventor： Renate Hofmann ,  Carsten Ahrens ,  Wolfgang Klein ,  Alexander Glas

IPC: H01L27/22 ,  H01L49/02 ,  H01F27/28

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01F41/046 ,  H01F2017/0066 ,  H01L23/5227 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.

Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底之内和/或之上形成第一电感线圈。 第一电感线圈形成在衬底的顶侧附近。 第一沟槽形成在与第一电感线圈相邻的衬底内。 至少部分地用磁性填充材料填充第一沟槽。 至少第一电感线圈下面的衬底的第一部分变薄。 背面磁性层形成在基板的第一部分之下。 背面磁性层和磁性填充材料形成第一电感线圈的磁芯区域的至少一部分。

公开(公告)号：US08952489B2

公开(公告)日：2015-02-10

申请号：US13647740

申请日：2012-10-09

Applicant: Infineon Technologies AG

Inventor： Klaus Elian ,  Jens Pohl ,  Horst Theuss ,  Renate Hofmann ,  Alexander Glas ,  Carsten Ahrens

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/495 ,  H01L23/522 ,  H01L23/29

CPC classification number: H01L23/295 ,  H01F2017/0066 ,  H01F2017/0086 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5227 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2224/03 ,  H01L2924/00

Abstract: A semiconductor package includes a semiconductor chip, an inductor applied to the semiconductor chip. The inductor includes at least one winding. A space within the at least one winding is filled with a magnetic material.

Abstract translation: 半导体封装包括半导体芯片，施加到半导体芯片的电感器。 电感器包括至少一个绕组。 至少一个绕组内的空间填充有磁性材料。