公开(公告)号：US09331060B2

公开(公告)日：2016-05-03

申请号：US14617797

申请日：2015-02-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Joachim Mahler ,  Johannes Lodermeyer

IPC: H01L25/00 ,  H01L23/492 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56 ,  H01L25/07 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/071 ,  H01L25/072 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24135 ,  H01L2224/245 ,  H01L2224/40105 ,  H01L2224/40227 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.

公开(公告)号：US09184066B2

公开(公告)日：2015-11-10

申请号：US13678577

申请日：2012-11-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess ,  Bernd Roemer ,  Edward Fuergut

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/495 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

Abstract: A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括：载体; 芯片，其设置在所述载体上方，所述芯片包括一个或多个接触焊盘，其中所述一个或多个接触焊盘的第一接触焊盘与所述载体电接触; 至少部分地围绕所述芯片的第一封装材料; 以及至少部分地围绕所述第一包封材料的第二包封材料。

公开(公告)号：US20150060878A1

公开(公告)日：2015-03-05

申请号：US14535138

申请日：2014-11-06

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/495

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L29/2003 ,  H01L29/78 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/85801 ,  H01L2224/8585 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.

Abstract translation: 根据本发明的实施例，半导体封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘和多个引线的第二引线框架。 第二模板设置在第一模板上。 半导体芯片设置在第二裸片上。 半导体芯片在面向第二引线框架的第一面上具有多个接触区域。 多个接触区域耦合到多个引线。

公开(公告)号：US20140138803A1

公开(公告)日：2014-05-22

申请号：US13678577

申请日：2012-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess ,  Bernd Roemer ,  Edward Fuergut

IPC: H01L23/34 ,  H01L23/552 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/495 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

Abstract: A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括：载体; 芯片，其设置在所述载体上方，所述芯片包括一个或多个接触焊盘，其中所述一个或多个接触焊盘的第一接触焊盘与所述载体电接触; 至少部分地围绕所述芯片的第一封装材料; 以及至少部分地围绕所述第一包封材料的第二包封材料。

公开(公告)号：US20140097528A1

公开(公告)日：2014-04-10

申请号：US13645548

申请日：2012-10-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Gerhard Noebauer ,  Chooi Mei Chong

IPC: H01L23/495 ,  H01L23/488 ,  H01L23/00

CPC classification number: H01L23/495 ,  H01L23/488 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/37111 ,  H01L2224/37118 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15701 ,  H01L2924/15717 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15763 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.

Abstract translation: 提供芯片封装。 芯片封装包括芯片载体，电压源引线，感测端子和设置在芯片载体上的芯片。 芯片包括第一端子和第二端子，其中第一端子电接触芯片载体。 芯片封装还包括形成在第二端子上的导电元件，导电元件将第二端子电耦合到电压源引线和感测端子。