公开(公告)号：US20160196988A1

公开(公告)日：2016-07-07

申请号：US15070968

申请日：2016-03-15

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  John S. Guzek

IPC: H01L21/48 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/31053 ,  H01L21/50 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

公开(公告)号：US20160183604A1

公开(公告)日：2016-06-30

申请号：US15062867

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Sairam Agraharam ,  John S. Guzek ,  Christopher J. Jezewski

IPC: A41D1/00 ,  G06F17/30 ,  H04N5/44 ,  G06K9/62 ,  H04N5/225 ,  H04N5/232

CPC classification number: A41D1/002 ,  G06F16/58 ,  G06K9/6215 ,  H04N5/225 ,  H04N5/2252 ,  H04N5/23238 ,  H04N5/23293 ,  H04N5/44 ,  H04N2101/00

Abstract: A wearable image sensor is described. In one example an apparatus includes a camera attached to a garment to capture an image of a view of an area surrounding a user that is wearing the garment, the image including an item. A data interface is attached to the garment and coupled to the camera to send the camera image to an external device and to receive description information about the item from the external device. A power supply is attached to the garment and coupled to the camera and the data interface to power the camera and the data interface. The apparatus presents the received description information to a user of the garment.

Abstract translation: 描述了可戴式图像传感器。 在一个示例中，一种装置包括附接到衣服的照相机，以捕获穿着服装的使用者周围的区域的视图的图像，该图像包括物品。 将数据接口连接到衣服并且耦合到相机以将照相机图像发送到外部设备并从外部设备接收关于该物品的描述信息。 电源被连接到衣服并且耦合到相机和数据接口以为相机和数据接口供电。 该装置将接收到的描述信息呈现给服装的用户。

公开(公告)号：US20160181207A1

公开(公告)日：2016-06-23

申请号：US15055120

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  John S. Guzek ,  Adel A. Elsherbini ,  Nitin Ashok Deshpande

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/568 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/81

Abstract: An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a mold compound is formed over a semiconductor die, the die being over a front side redistribution layer on a side opposite the mold compound, the redistribution layer extending past the die and the mold compound extending around the die to contact the redistribution layer. A plurality of vias are formed in the mold compound vertically toward the redistribution layer, the vias being outside of the die, wherein the bottoms of the vias are over a ground layer of the front side redistribution layer. A continuous conductive shielding film is applied over the mold compound and into the vias, wherein the shielding film in some of the vias directly connects to the ground layer and wherein the shielding film in some of the vias does not directly connect to the ground layer, the redistribution layer connecting the metal film to an external ground so that the vias form a shield.

Abstract translation: 半导体芯片封装描述了电磁干扰屏蔽。 在一些实施例中，在半导体管芯上形成模具化合物，模具位于与模具化合物相对的一侧上的正面再分配层上，再分配层延伸超过模具，并且模具化合物围绕模具延伸以接触再分布 层。 多个通孔在模具化合物中垂直地朝向再分布层形成，通孔在模具外部，其中通孔的底部在正面再分布层的接地层之上。 将连续导电屏蔽膜施加到模具化合物上并穿过通孔，其中一些通孔中的屏蔽膜直接连接到接地层，并且其中一些通孔中的屏蔽膜不直接连接到接地层， 再分配层将金属膜连接到外部地面，使得通孔形成屏蔽。

公开(公告)号：US09257380B2

公开(公告)日：2016-02-09

申请号：US14624873

申请日：2015-02-18

Applicant: Intel Corporation

Inventor： Ravi K. Nalla ,  John S. Guzek ,  Javier Soto Gonzalez ,  Drew W. Delaney ,  Hamid R. Azimi

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56 ,  H01L21/02 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

公开(公告)号：US20160027757A1

公开(公告)日：2016-01-28

申请号：US14875247

申请日：2015-10-05

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/367

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

公开(公告)号：US20150340353A1

公开(公告)日：2015-11-26

申请号：US14818902

申请日：2015-08-05

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Abstract translation: 本文通常描述用于局部高密度衬底布线的系统和方法的实施例。 在一个或多个实施例中，一种装置包括介质，第一和第二电路元件，互连元件和电介质层。 该介质可以包括其中的低密度路由。 互连元件可以嵌入在介质中，并且可以在其中包括多个导电构件，导电构件可以电耦合到第一电路元件和第二电路元件。 互连元件可以包括其中的高密度路由。 电介质层可以在互连裸片上方，电介质层包括通过其中的第一和第二电路元件。

公开(公告)号：US09001520B2

公开(公告)日：2015-04-07

申请号：US13625406

申请日：2012-09-24

Applicant: Intel Corporation

Inventor： Qing Ma ,  Johanna M. Swan ,  Robert Starkston ,  John S. Guzek ,  Robert L. Sankman ,  Aleksandar Aleksov

IPC: H05K1/18 ,  H01L21/56 ,  H01L23/15 ,  H01L23/538 ,  H01L23/00 ,  H05K3/46 ,  H01L23/498

CPC classification number: H01L23/5386 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4688 ,  H05K2201/017 ,  H05K2203/1469 ,  Y10T156/1057 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

Abstract translation: 本说明书的实施例涉及制造微电子结构的领域。 微电子结构可以包括与轨迹路由结构分开形成的玻璃布线结构，其中玻璃布线结构以层叠或嵌入的形式结合到迹线布线基板中。 还公开了微电子封装的实施例，其包括设置在微电子衬底的玻璃布线结构附近并通过多个互连与微电子衬底耦合的至少一个微电子器件。 此外，公开了微电子结构的实施例，其包括嵌入微电子密封剂内的至少一个微电子器件，该微电子器件具有连接到微电子密封剂的玻璃布线结构和形成在玻璃布线结构上的迹线布线结构。

公开(公告)号：US08969140B2

公开(公告)日：2015-03-03

申请号：US13966806

申请日：2013-08-14

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  John S. Guzek

IPC: H01L21/00 ,  H01L23/02 ,  H01L23/522 ,  H01L21/683 ,  H01L23/538 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16 ,  H01L21/50

CPC classification number: H01L21/4853 ,  H01L21/31053 ,  H01L21/50 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Abstract translation: 重构的晶片包括具有平坦表面的刚性块和平行于平坦表面设置的基底表面。 多个骰子嵌入刚体中。 多个骰子包括通过与平坦表面共面露出的端子。 形成重构的晶片的过程包括去除刚性质量块中的一些以露出端子，同时将多个裸片保持在刚性质量块中。 形成设备的过程包括将一个设备与重构的晶片分开。

公开(公告)号：US08912670B2

公开(公告)日：2014-12-16

申请号：US13631205

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

IPC: H01L23/28 ,  H01L23/10

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract translation: 一个实例包括包括具有下模表面的微电子管芯，平行于下模表面的上模表面和管芯侧的管芯封装，该微电子管芯包括有源区和非活性区。 该实施例可选地包括具有较低散热器表面的散热器，平行于下部散热器表面的上部散热器表面和至少一个散热器侧，散热器布置在热电连接的微电子管芯的上表面上 具有裸片的非活性区域并与活性区电绝缘。 该实施例可选地包括封装模具侧和散热器侧和下部散热器表面的封装材料，该封装材料包括基本上平行于模具下表面的下表面和基本上平行于模具上表面的上表面。

公开(公告)号：US11257688B2

公开(公告)日：2022-02-22

申请号：US16871503

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  John S. Guzek

IPC: H01L21/00 ,  H01L23/02 ,  H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L23/64 ,  H01L25/16 ,  H01L21/50 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.