公开(公告)号：US20160315047A1

公开(公告)日：2016-10-27

申请号：US15200554

申请日：2016-07-01

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Abstract translation: 在具有穿过衬底（104）并且突出在衬底上方的导电通路（114）的微电子部件中，导电特征（120E.A，120E.B）设置在衬底上方，该衬底环绕导电通孔突起（114'） ）以形成电容器，电磁屏蔽以及可能的其他元件。 还提供了其它特征和实施例。

公开(公告)号：US09397038B1

公开(公告)日：2016-07-19

申请号：US14633746

申请日：2015-02-27

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L21/44 ,  H01L23/04 ,  H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Abstract translation: 在具有穿过衬底（104）并且突出在衬底上方的导电通路（114）的微电子部件中，导电特征（120E.A，120E.B）设置在衬底上方，该衬底环绕导电通孔突起（114'） ）以形成电容器，电磁屏蔽以及可能的其他元件。 还提供了其它特征和实施例。

公开(公告)号：US09349707B1

公开(公告)日：2016-05-24

申请号：US14609896

申请日：2015-01-30

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC: H01L23/02 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L23/13 ,  H01L23/34 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16057 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/4502 ,  H01L2224/48138 ,  H01L2224/48148 ,  H01L2224/48165 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/49174 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1511 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3701 ,  H01L2224/45099

Abstract: An apparatus relates generally to a microelectronic assembly. In this apparatus, a first substrate and a second substrate each have opposing surfaces. Contact arrangements are disposed on a surface of the first substrate, including: first contacts disposed as a ring to provide a first array of the contact arrangements on such surface; and second contacts disposed interior to the ring of the first contacts to provide a second array of the contact arrangements on the first surface. The first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies. The second microelectronic dies are disposed below the first microelectronic dies in same a package as the first microelectronic dies. The first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.

Abstract translation: 装置一般涉及微电子组件。 在该装置中，第一基板和第二基板各自具有相对的表面。 接触装置设置在第一基板的表面上，包括：作为环设置的第一触点，以在该表面上提供接触装置的第一阵列; 以及第二触点，其设置在第一触头的环的内部，以在第一表面上提供接触装置的第二阵列。 第一触点和第二触点用于与第一微电子管芯和第二微电子管芯互连。 第二微电子管芯以与第一微电子管芯相同的封装设置在第一微电子管芯的下方。 第一微电子管芯和第二微电子管芯包括至少两个等级，用于共同共享第一微触点和第一微电子管芯与第二微电子管芯之间的第二触点。

公开(公告)号：US09337170B1

公开(公告)日：2016-05-10

申请号：US14609878

申请日：2015-01-30

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus relates generally to a microelectronic assembly. In such an apparatus, a contact arrangements are disposed on a first surface of a first substrate, including first contacts disposed as a first ring array; second contacts disposed interior to the first contacts as a second ring array; third contacts disposed interior to the second contacts as a third ring array; and fourth contacts disposed interior to the third contacts on the first surface as an innermost array. The first ring array, the second ring array, and the third ring array are concentric rings with the innermost array in a central region of the concentric rings. The first contacts and the fourth contacts are for interconnection with first microelectronic dies. The second contacts and the third contacts are for interconnection with second microelectronic dies.

Abstract translation: 装置一般涉及微电子组件。 在这种装置中，接触装置设置在第一基板的第一表面上，包括设置为第一环阵列的第一触点; 第二触点设置在第一触点内部作为第二环阵列; 设置在第二触点内部的第三触点作为第三环阵列; 以及第四触点，其设置在第一表面上的作为最内侧阵列的第三触点的内部。 第一环阵列，第二环阵列和第三环阵列是在同心环的中心区域中具有最内阵列的同心环。 第一触点和第四触点用于与第一微电子模具互连。 第二触点和第三触点用于与第二微电子管芯互连。

公开(公告)号：US20150041988A1

公开(公告)日：2015-02-12

申请号：US13962349

申请日：2013-08-08

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Zhuowen Sun

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/7682 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

Abstract translation: 互连部件包括半导体材料层，其具有第一表面和与第一表面相对的第二表面，并且在第一方向上间隔开。 至少两个金属化通孔延伸穿过半导体材料层。 所述至少两个金属化通孔中的第一对在与第一方向正交的第二方向上彼此间隔开。 半导体层中的第一绝缘通孔从第一表面延伸到第二表面。 绝缘通孔被定位成使得绝缘通孔的几何中心在与第二方向正交的两个平面之间并且穿过第一对至少两个金属化通孔中的每一个。 电介质材料至少部分地填充第一绝缘通孔或至少部分地封闭绝缘通孔中的空隙。

公开(公告)号：US10700002B2

公开(公告)日：2020-06-30

申请号：US16446822

申请日：2019-06-20

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Zhuowen Sun

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/498 ,  H01L21/768 ,  H01L23/14 ,  H01L21/48

Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

公开(公告)号：US10559537B2

公开(公告)日：2020-02-11

申请号：US16127110

申请日：2018-09-10

Applicant: Invensas Corporation

Inventor： Abiola Awujoola ,  Zhuowen Sun ,  Wael Zohni ,  Ashok S. Prabhu ,  Willmar Subido

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L25/03 ,  H01L25/065

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

公开(公告)号：US10522457B2

公开(公告)日：2019-12-31

申请号：US16238786

申请日：2019-01-03

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/04 ,  H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/8234

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, one or more conductive features (120E.A, 120E.B, or both) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US10177086B2

公开(公告)日：2019-01-08

申请号：US15952935

申请日：2018-04-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L21/8234

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US20180240773A1

公开(公告)日：2018-08-23

申请号：US15959619

申请日：2018-04-23

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Abiola Awujoola ,  Ashok S. Prabhu ,  Christopher W. Lattin ,  Zhuowen Sun

IPC: H01L23/00 ,  H05K1/02 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L24/49 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/17 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/11334 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0284 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.