公开(公告)号：US20130175694A1

公开(公告)日：2013-07-11

申请号：US13345485

申请日：2012-01-06

Applicant: Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： Ying-Ching Shih ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L21/58 ,  H01L23/485 ,  H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/83

Abstract: A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.

Abstract translation: 一种方法包括在衬底上形成电介质层，在电介质层上形成互连结构，以及将管芯结合到互连结构。 然后去除衬底，并对电介质层进行图案化。 连接器形成在电介质层的表面，其中连接器电耦合到管芯。

公开(公告)号：US20130154062A1

公开(公告)日：2013-06-20

申请号：US13328746

申请日：2011-12-16

Applicant: Jing-Cheng Lin ,  Ying-Da Wang ,  Li-Chung Kuo ,  Szu Wei Lu

Inventor： Jing-Cheng Lin ,  Ying-Da Wang ,  Li-Chung Kuo ,  Szu Wei Lu

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A die having a ledge along a sidewall, and a method of forming the die, is provided. A method of packaging the die is also provided. A substrate, such as a processed wafer, is diced by forming a first notch having a first width, and then forming a second notch within the first notch such that the second notch has a second width less than the first width. The second notch extends through the substrate, thereby dicing the substrate. The difference in widths between the first width and the second width results in a ledge along the sidewalls of the dice. The dice may be placed on a substrate, e.g., an interposer, and underfill placed between the dice and the substrate. The ledge prevents or reduces the distance the underfill is drawn up between adjacent dice. A molding compound may be formed over the substrate.

Abstract translation: 提供具有沿侧壁的凸缘的模具和形成模具的方法。 还提供了一种包装模具的方法。 通过形成具有第一宽度的第一凹口，然后在第一凹口内形成第二凹槽，使得第二凹槽具有小于第一宽度的第二宽度，来切割诸如经处理晶片的基底。 第二凹口延伸穿过衬底，从而切割衬底。 第一宽度和第二宽度之间的宽度差导致沿着骰子的侧壁的凸缘。 骰子可以放置在基底上，例如插入物，以及放置在骰子和基底之间的底部填充物。 凸缘防止或减少底部填充物在相邻骰子之间的距离。 可以在基材上形成模塑料。

公开(公告)号：US20130122659A1

公开(公告)日：2013-05-16

申请号：US13296922

申请日：2011-11-15

Applicant: Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/56

CPC classification number: H01L24/97 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method comprises attaching a first side of an interposer on a carrier wafer. The first side of the interposer comprises a plurality of bumps. The carrier wafer comprises a plurality of cavities formed in the carrier wafer. Each bump on the first side of the interposer can fit into its corresponding cavity on the carrier wafer. Subsequently, the method comprises attaching a semiconductor die on the second side of the interposer to form a wafer stack, detaching the wafer stack from the carrier wafer and attaching the wafer stack to a substrate.

Abstract translation: 一种方法包括将插入件的第一侧附着在载体晶片上。 插入器的第一侧包括多个凸块。 载体晶片包括形成在载体晶片中的多个空腔。 插入器的第一侧上的每个凸块可以装配到载体晶片上的相应空腔中。 随后，该方法包括在插入器的第二侧上附加半导体管芯以形成晶片堆叠，将晶片堆叠与载体晶片分离并将晶片堆叠连接到基板。

公开(公告)号：US20130075937A1

公开(公告)日：2013-03-28

申请号：US13246556

申请日：2011-09-27

Applicant: Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

Inventor： Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/28 ,  H01L21/50 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.

Abstract translation: 用于在晶片插入件上的模具上进行模制的方法和装置。 一种方法包括接收具有管芯侧面和相对侧的插入件组件，所述插入件组件包括安装在所述插入件的裸片侧上的两个或多个集成电路管芯，所述插入器组件具有形成在所述插入件的裸片侧上的两个或更多个集成 电路模具; 在所述两个或更多个集成电路管芯之间的空间之一中在所述插入器组件的管芯侧上安装至少一个应力释放特征; 以及使用模具化合物模制所述集成电路模具，围绕所述两个或更多个集成电路管芯的所述模具化合物以及所述至少一个应力释放特征。 公开了一种装置，其集成电路安装在插入件的裸片侧，集成电路之间的应力消除特征和集成电路上的模具化合物。

公开(公告)号：US20130049234A1

公开(公告)日：2013-02-28

申请号：US13216825

申请日：2011-08-24

Applicant: Jing-Cheng Lin ,  Chih-Wei Wu ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chih-Wei Wu ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/78 ,  H01L23/28

CPC classification number: H01L23/49816 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

Abstract translation: 提供了一种用于将基底分离成单个模具的方法和装置，并且提供了所得到的结构。 在衬底内形成诸如非晶层的改性层。 可以使用聚焦在衬底内的激光来产生修饰层。 改性层产生比周围的基材更容易破裂的相对较弱的区域。 结果，衬底可以被拉开到分开的部分中，从而沿着修饰层裂开衬底。 在分离之前或之后，骰子或其它组分可附着于基底。

公开(公告)号：US09691706B2

公开(公告)日：2017-06-27

申请号：US13452140

申请日：2012-04-20

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/544 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/742 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2223/54426 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/24991 ,  H01L2224/82005 ,  H01L2224/82106 ,  H01L2224/8213 ,  H01L2224/82132 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/00

Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

公开(公告)号：US09662812B2

公开(公告)日：2017-05-30

申请号：US13485307

申请日：2012-05-31

Applicant: Chih-Hao Chen ,  Hsien-Wen Liu ,  Yi-Lin Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Chih-Hao Chen ,  Hsien-Wen Liu ,  Yi-Lin Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: B29C43/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: B29C43/18 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/1531 ,  H01L2924/157 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature.

公开(公告)号：US09153506B2

公开(公告)日：2015-10-06

申请号：US13542896

申请日：2012-07-06

Applicant: Chien Rhone Wang ,  Kewei Zuo ,  Chen-Hua Yu ,  Jing-Cheng Lin ,  Yen-Hsin Liu

Inventor： Chien Rhone Wang ,  Kewei Zuo ,  Chen-Hua Yu ,  Jing-Cheng Lin ,  Yen-Hsin Liu

IPC: G06F19/00 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L22/20 ,  H01L21/76898 ,  H01L22/12

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.

Abstract translation: 本公开提供了用于形成具有一个或多个贯穿硅通孔（TSV）特征的IC结构的集成电路（IC）制造方法的一个实施例。 IC制作方法包括执行多个处理步骤; 从多个处理步骤收集物理计量数据; 基于所述物理测量数据从所述多个处理步骤收集虚拟测量数据; 基于物理测量数据和虚拟测量数据，为IC结构生成产量预测; 以及基于所述产量预测在较早的处理步骤中识别动作。

公开(公告)号：US09117682B2

公开(公告)日：2015-08-25

申请号：US13270850

申请日：2011-10-11

Applicant: Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L21/78 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Abstract translation: 公开了封装半导体器件的方法及其结构。 在一个实施例中，一种封装半导体器件的方法包括提供载体晶片，提供多个管芯，以及在载体晶片上形成管芯洞穴材料。 在模具洞穴材料中形成多个模具洞穴。 将多个模具中的至少一个放置在模具洞穴材料中的多个模具洞穴的每一个中。 形成多个封装，所述多个封装中的每个封装形成在所述多个管芯中的相应的至少一个管芯上。

公开(公告)号：US08803316B2

公开(公告)日：2014-08-12

申请号：US13311692

申请日：2011-12-06

Applicant: Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

Inventor： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/11011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/73204 ,  H01L2924/01028 ,  H01L2924/0132 ,  H01L2924/067 ,  H01L2924/0705 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

Abstract translation: 一种器件包括具有正面和背面的衬底，从衬底的背面延伸到前侧的通孔，以及位于衬底的背面和通孔上方的导电焊盘。 导电垫具有基本平坦的顶表面。 导电凸块在基本上平坦的顶表面上方具有非平面的顶表面，并且与通孔对准。 导电凸块和导电垫由相同的材料形成。 在导电凸块和导电垫之间不形成界面。