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    Amplifier circuit with static consumption control and corresponding control method
    33.
    发明授权
    Amplifier circuit with static consumption control and corresponding control method 有权
    放大器电路具有静态消耗控制和相应的控制方式

    公开(公告)号：US09484872B1

    公开(公告)日：2016-11-01

    申请号：US14969042

    申请日：2015-12-15

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Antonino Conte ,  Alberto Jose' Di Martino

    IPC: H03F3/45 ,  H03M1/66 ,  G11C16/12 ,  G11C5/14

    CPC classification number: H03F3/45179 ,  G11C5/145 ,  G11C16/12 ,  H03F3/3027 ,  H03F3/45659 ,  H03F3/45748 ,  H03F3/45973 ,  H03F2203/45116 ,  H03F2203/45424 ,  H03F2203/45431 ,  H03M1/66

    Abstract: An amplifier circuit may include an input amplification stage comprising a first amplifier having first and second differential inputs and a first output, and a second amplifier having first and second differential inputs and a second output. The amplifier circuit also includes an output amplification stage having first and second inputs respectively coupled to the first and second outputs of the input amplification stage, and an output configured to supply an output voltage based upon the input voltage by an amplification factor. The amplifier circuit comprises a feedback stage with a common-mode control stage configured to implement a comparison between the first differential voltage and the second differential voltage, and a reference voltage, and generate respective regulation currents on the first and second inputs of the output amplification stage to compensate for a common-mode variation of the first differential voltage and the second differential voltage.

    Abstract translation: 放大器电路可以包括输入放大级，其包括具有第一和第二差分输入和第一输出的第一放大器，以及具有第一和第二差分输入和第二输出的第二放大器。 放大器电路还包括输出放大级，其具有分别耦合到输入放大级的第一和第二输出的第一和第二输入以及被配置为基于输入电压提供放大因子的输出电压的输出。 放大器电路包括具有共模控制级的反馈级，配置为实现第一差分电压和第二差分电压之间的比较以及参考电压，并且在输出放大的第一和第二输入上产生相应的调节电流 以补偿第一差分电压和第二差分电压的共模变化。

    Error correction in memory devices by multiple readings with different references
    34.
    发明授权
    Error correction in memory devices by multiple readings with different references 有权
    通过不同参考的多个读数对存储器件进行错误校正

    公开(公告)号：US09430328B2

    公开(公告)日：2016-08-30

    申请号：US14597845

    申请日：2015-01-15

    Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS PTE LTD

    Inventor： Antonino Conte ,  Kailash Khairnar

    IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F11/08 ,  G11C13/00

    CPC classification number: G06F11/1068 ,  G06F11/08 ,  G06F11/1048 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/52 ,  G11C2013/0054

    Abstract: A memory device may include memory cells. The method may include receiving a request of reading a selected data word associated with a selected code word stored with an error correction code, and reading a first code word representing a first version of the selected code word by comparing a state of each selected memory cell with a first reference. The method may include verifying the first code word, setting the selected code word according to the first code word in response to a positive verification, reading at least one second code word representing a second version of the selected code word, verifying the second code word, and setting the selected code word according to the second code word in response to a negative verification of the first code word and to a positive verification of the second code word.

    Abstract translation: 存储器件可以包括存储器单元。 该方法可以包括：接收读取与通过纠错码存储的所选码字相关联的所选择的数据字的请求，以及通过比较所选择的存储单元的状态来读取表示所选码字的第一版本的第一码字 第一个参考。 该方法可以包括验证第一代码字，响应于正验证，根据第一代码字设置所选择的代码字，读取表示所选代码字的第二版本的至少一个第二代码字，验证第二代码字 并且响应于第一代码字的否定验证和第二代码字的肯定验证，根据第二代码字设置所选择的代码字。

    Decoding architecture and method for phase change non-volatile memory devices
    35.
    发明授权
    Decoding architecture and method for phase change non-volatile memory devices 有权
    相变非易失性存储器件的解码架构和方法

    公开(公告)号：US08982615B2

    公开(公告)日：2015-03-17

    申请号：US13780280

    申请日：2013-02-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino Conte ,  Francesca Grande ,  AlbertoJose′ Dimartino ,  Alfredo Signorello

    IPC: G11C11/00 ,  G11C8/00 ,  G11C13/00 ,  G11C8/12 ,  G11C7/12 ,  G11C8/10 ,  G11C5/14

    CPC classification number: G11C13/0009 ,  G11C5/146 ,  G11C7/12 ,  G11C8/10 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2207/005

    Abstract: A decoding system for a phase change non-volatile memory device having a memory array may include a column decoder that selects at least one column of the memory array during programming operations. The decoding system includes a selection circuit that includes selection switches on a number of hierarchical decoding levels for defining a conductive path between at least one column and a driving stage. A biasing circuit may supply biasing signals to the selection switches for defining the first conductive path and bringing the selected column to a programming voltage value. The programming selection circuit may have protection elements between columns and the selection switches. The selection switches and the protection elements may include metal oxide semiconductor (MOS) transistors having an upper threshold voltage level lower than the programming voltage.

    Abstract translation: 具有存储器阵列的相变非易失性存储器件的解码系统可以包括在编程操作期间选择存储器阵列的至少一列的列解码器。 解码系统包括选择电路，其包括用于限定至少一个列和驱动级之间的导电路径的多个分层解码级别的选择开关。 偏置电路可以向选择开关提供偏置信号，用于限定第一导电路径并使所选列进入编程电压值。 编程选择电路可以具有列和选择开关之间的保护元件。 选择开关和保护元件可以包括具有比编程电压低的上阈值电压电平的金属氧化物半导体（MOS）晶体管。

    Driver circuit for phase-change memory cells and method of driving phase-change memory cells
    36.
    发明授权
    Driver circuit for phase-change memory cells and method of driving phase-change memory cells 有权

    公开(公告)号：US12148470B2

    公开(公告)日：2024-11-19

    申请号：US17814442

    申请日：2022-07-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Agatino Massimo Maccarrone ,  Antonino Conte ,  Francesco Tomaiuolo ,  Michelangelo Pisasale ,  Marco Ruta

    IPC: G11C13/00

    Abstract: In an embodiment a circuit includes a plurality of memory cells, wherein each memory cell includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal, a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses and at least one current generator circuit configured to inject a compensation current for the programming currents into the common control node.

    RING OSCILLATOR CIRCUIT
    37.
    发明申请
    RING OSCILLATOR CIRCUIT 有权

    公开(公告)号：US20220399880A1

    公开(公告)日：2022-12-15

    申请号：US17830864

    申请日：2022-06-02

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Alps) SAS

    Inventor： Antonino Conte ,  Marco Ruta ,  Michelangelo Pisasale ,  Thomas Jouanneau

    IPC: H03K3/03 ,  H03K3/011 ,  H03K3/012 ,  H03K3/014

    Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

    NON-VOLATILE PHASE-CHANGE MEMORY DEVICE INCLUDING A DISTRIBUTED ROW DECODER WITH N-CHANNEL MOSFET TRANSISTORS AND RELATED ROW DECODING METHOD
    38.
    发明申请
    NON-VOLATILE PHASE-CHANGE MEMORY DEVICE INCLUDING A DISTRIBUTED ROW DECODER WITH N-CHANNEL MOSFET TRANSISTORS AND RELATED ROW DECODING METHOD 有权

    公开(公告)号：US20220284954A1

    公开(公告)日：2022-09-08

    申请号：US17667080

    申请日：2022-02-08

    Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

    Inventor： Antonino Conte ,  Alin Razafindraibe ,  Francesco Tomaiuolo ,  Thibault Mortier

    IPC: G11C13/00

    Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage configured to decouple from or couple to a node at a first reference potential each wordline that extends through the group of memory portions, when the wordline is respectively selected or deselected, so as to impose on each wordline, when deselected, a deselection voltage, a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage being configured to locally couple each wordline that extends through the group of memory portions, when selected, to a node at a second reference potential, so as to impose locally a selection voltage on the wordline, wherein each pull-down stage is further configured to locally decouple from the node at the second reference potential each wordline that extends through the group of memory portions, when deselected; and a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage having, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type.

    Floating boosted pre-charge scheme for sense amplifiers
    40.
    发明授权
    Floating boosted pre-charge scheme for sense amplifiers 有权

    公开(公告)号：US10658048B2

    公开(公告)日：2020-05-19

    申请号：US16104001

    申请日：2018-08-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino Conte ,  Loredana Chiaramonte ,  Anna Rita Maria Lipani

    IPC: G11C16/28 ,  G11C16/24 ,  G11C16/04

    Abstract: A sense structure includes: a sense amplifier core configured to compare a measurement current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.

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