公开(公告)号：US07452568B2

公开(公告)日：2008-11-18

申请号：US11049846

申请日：2005-02-04

申请人： Gareth Hougham ,  Leena Paivikki Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelorme ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

发明人： Gareth Hougham ,  Leena Paivikki Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelorme ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

IPC分类号： B05D3/12 ,  B05D1/42

CPC分类号： H05K3/4053 ,  B05D1/002 ,  H01L21/486 ,  H01L21/76898 ,  H05K2201/09509 ,  H05K2203/1554

摘要： The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

摘要翻译： 本公开总体上涉及半导体，集成电路，特别是但不限于，用于填充高纵横比通孔和沟槽的离心方法，其具有粉末，浆料，材料的悬浮液，以充当导电的结构 支撑或电子部件的保护构件。

公开(公告)号：US07435627B2

公开(公告)日：2008-10-14

申请号：US11201572

申请日：2005-08-11

申请人： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L21/82

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US20080182359A1

公开(公告)日：2008-07-31

申请号：US12056852

申请日：2008-03-27

申请人： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L21/00

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US07170187B2

公开(公告)日：2007-01-30

申请号：US10711185

申请日：2004-08-31

申请人： William E. Bernier ,  Marie S. Cole ,  Mukta G. Farooq ,  John U. Knickerbocker ,  Tasha E. Lopez ,  Roger A. Quon ,  David J. Welsh

发明人： William E. Bernier ,  Marie S. Cole ,  Mukta G. Farooq ,  John U. Knickerbocker ,  Tasha E. Lopez ,  Roger A. Quon ,  David J. Welsh

IPC分类号： H01L23/48

CPC分类号： H05K3/321 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13339 ,  H01L2224/13464 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H05K2201/0212 ,  H05K2201/0248 ,  H05K2201/0373 ,  H05K2201/1025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00015 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.

摘要翻译： 公开了用于将集成电路器件连接到器件载体的层压（或非层叠）导电互连，其中导电互连包括交替的金属层和聚合物层。 此外，聚合物可以包括枝晶，来自载体或器件的金属突起，和/或聚合物外部的胶束刷。 聚合物层包括金属颗粒，并且交替的金属层和聚合物层形成立方体结构或圆柱形结构。

公开(公告)号：US06607620B2

公开(公告)日：2003-08-19

申请号：US09757071

申请日：2001-01-08

申请人： John U. Knickerbocker ,  Govindarajan Natarajan

发明人： John U. Knickerbocker ,  Govindarajan Natarajan

IPC分类号： B32B3118

CPC分类号： B32B18/00 ,  B32B37/22 ,  B32B38/04 ,  B32B2038/042 ,  B32B2305/38 ,  B32B2305/77 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/38 ,  C04B2237/50 ,  C04B2237/56 ,  C04B2237/561 ,  C04B2237/567 ,  C04B2237/62 ,  C04B2237/66 ,  C04B2237/68 ,  C04B2237/702 ,  C04B2237/704 ,  H01L21/4857 ,  H05K1/0306 ,  H05K3/00 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2203/0169 ,  Y10T156/1052 ,  Y10T156/1057 ,  Y10T156/108 ,  Y10T428/161 ,  Y10T428/23 ,  Y10T428/24793 ,  Y10T428/24926

摘要： A method of processing greensheets for use as microelectronic substrates comprises providing a greensheet having a width, a length and a thickness, bonding to the greensheet, within the greensheet width and length, a frame adapted to constrain movement of the greensheet within the frame, processing the greensheet and bonded frame, and removing the frame from the processed greensheet. The processing of the greensheet and bonded frame may include punching vias in the greensheet, filling the vias in the greensheet with conductive material, patterning the greensheet by applying conductive paste to the vias and greensheet surface, stacking the patterned greensheet and bonded frame with at least one other patterned greensheet and bonded frame, and laminating the greensheets. The frame is preferably removed from the processed greensheet after laminating the greensheets, and before the laminated greensheets are subsequently sintered. The bonding of the frame to the greensheet may be by lamination or by an adhesive, or by other means. Preferably, the frame has a thickness less than the greensheet thickness. The frame preferably has a plurality of members subdividing the greensheet into a plurality of areas, with each area being completely surrounded by frame members. The frame may be applied to one side of the greensheet, and pressed into the greensheet side such that the frame and greensheet side are substantially coplanar.

摘要翻译： 处理用作微电子基板的纸屑的方法包括在毛坯宽度和长度内提供具有宽度，长度和厚度粘合到毛坯上的毛坯，适于限制毛坯在框架内的移动的框架，加工 毛坯和粘合框架，并从加工的毛坯上移除框架。 毛坯和粘合框架的加工可以包括毛坯中的穿孔，用导电材料填充毛坯中的通孔，通过将导电浆涂布到通孔和毛坯表面来图案化毛坯，至少堆叠图案化的毛坯和粘合的框架 一个其他图案化的毛坯和粘合框架，并且层压绿叶片。 在层压毛坯之后，并且在随后烧结层压的刮板之前，优选地将骨架从加工的毛坯板上去除。 框架与毛坯的接合可以通过层压或通过粘合剂或其他方式进行。 优选地，框架具有小于毛坯厚度的厚度。 框架优选地具有将毛坯细分成多个区域的多个构件，每个区域被框架构件完全包围。 框架可以施加到毛坯的一侧，并且被压入毛坯一侧，使得框架和毛坯面基本上共面。

公开(公告)号：US06461493B1

公开(公告)日：2002-10-08

申请号：US09472136

申请日：1999-12-23

申请人： Mukta S. Farooq ,  Shaji Farooq ,  John U. Knickerbocker ,  Robert A. Rita ,  Srinivasa N. Reddy

发明人： Mukta S. Farooq ,  Shaji Farooq ,  John U. Knickerbocker ,  Robert A. Rita ,  Srinivasa N. Reddy

IPC分类号： C25D502

CPC分类号： H05K3/445 ,  H01G4/10 ,  H05K1/053 ,  H05K1/162 ,  H05K3/4069 ,  H05K2201/09554 ,  H05K2203/0315 ,  H05K2203/1142

摘要： A process for fabricating a structure using a metal carrier and forming a double capacitor structure. The process comprises forming a first via hole through the metal carrier, forming a dielectric layer around the metal carrier and inside the first via hole, forming a second via hole through the dielectric layer and the metal carrier, and filling at least one of the via holes with conductive material. In one preferred embodiment, the process further comprises forming a third via hole through the metal carrier before the forming of a dielectric layer, wherein the dielectric layer is formed around the metal carrier, inside the first via hole, and inside the third via hole. The first via hole, the second via hole, and the third via hole are all filled with a conductive material. In one preferred embodiment, the dielectric layer comprises a top surface opposed to a bottom surface, and electrodes are formed on at least one of the top surface and the bottom surface of the dielectric layer.

摘要翻译： 一种使用金属载体制造结构并形成双电容器结构的方法。 该工艺包括形成通过金属载体的第一通孔，在金属载体周围形成电介质层，并在第一通孔内部形成介电层，形成穿过电介质层和金属载体的第二通孔，并填充至少一个通孔 孔与导电材料。 在一个优选实施例中，该方法还包括在形成电介质层之前通过金属载体形成第三通孔，其中介电层围绕金属载体形成在第一通孔的内部，以及在第三通孔的内部。 第一通孔，第二通孔和第三通孔均填充有导电材料。 在一个优选实施例中，电介质层包括与底表面相对的顶表面，并且在介电层的顶表面和底表面中的至少一个上形成电极。

公开(公告)号：US06402866B1

公开(公告)日：2002-06-11

申请号：US09410474

申请日：1999-09-30

申请人： Jon A. Casey ,  John U. Knickerbocker ,  David C. Long ,  Brenda L. Peterson

发明人： Jon A. Casey ,  John U. Knickerbocker ,  David C. Long ,  Brenda L. Peterson

IPC分类号： B32B3126

CPC分类号： H05K3/046 ,  H01L21/4867 ,  Y10T29/49163

摘要： A method and apparatus are provided for forming metal circuit patterns and other designs on greensheets and other substrates. The method and apparatus utilize a metal containing transfer sheet whereby selected portions of the metal containing transfer sheet are transferred to the greensheet forming the desired circuit pattern and then the transfer sheet removed. The metal containing transfer sheet may contain a release layer. Transfer methods include stamping, hot rolling, laser beam, heat, etc. and combinations thereof The transfer sheet may also have a stratified or graded vertical profile so that different conductivities or other circuit properties (transfer sheet adhesion, etc.) may be obtained in the formed pattern on the substrate.

摘要翻译： 提供了一种方法和装置，用于在刮板和其它基底上形成金属电路图案和其它设计。 该方法和设备利用含金属的转印片，由此将含金属转印片的选定部分转移到形成所需电路图案的毛坯上，然后移除转印片。 含金属的转印片可以含有剥离层。 转印方法包括冲压，热轧，激光束，热等及其组合。转印片材还可以具有分层或分级的垂直轮廓，从而可以获得不同的电导率或其它电路性质（转印片粘合等） 衬底上形成的图案。

公开(公告)号：US06291272B1

公开(公告)日：2001-09-18

申请号：US09471563

申请日：1999-12-23

申请人： Ajay P. Giri ,  John U. Knickerbocker ,  David C. Long ,  Subhash L. Shinde ,  Lisa M. Studzinski ,  Rao V. Vallabhaneni

发明人： Ajay P. Giri ,  John U. Knickerbocker ,  David C. Long ,  Subhash L. Shinde ,  Lisa M. Studzinski ,  Rao V. Vallabhaneni

IPC分类号： H01L2144

CPC分类号： H01L21/4867 ,  H01L21/4857 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/15311

摘要： A process for fabricating a microelectronic structure. The process comprises processing a metal carrier having a top surface and a bottom surface, wherein the top surface and the bottom surface are processed to promote adhesion, forming a dielectric layer around the metal carrier, wherein the dielectric layer substantially covers the top surface and the bottom surface of the metal carrier, and applying a first patterned layer of conductive material to the microelectronic structure. In one preferred embodiment, the process further comprises comprising sintering the metal carrier, the dielectric layer, and the first patterned layer of conductive material. In one preferred embodiment, the process further comprises forming a via hole through the metal carrier before the forming of the dielectric layer around the metal carrier, wherein the forming of the dielectric layer comprises forming the dielectric layer inside the via hole.

摘要翻译： 一种制造微电子结构的方法。 该方法包括处理具有顶表面和底表面的金属载体，其中处理顶表面和底表面以促进粘附，在金属载体周围形成电介质层，其中电介质层基本上覆盖顶表面和 金属载体的底表面，以及将第一图案化的导电材料层施加到微电子结构。 在一个优选实施例中，该方法还包括包括烧结金属载体，电介质层和导电材料的第一图案化层。 在一个优选实施例中，该方法还包括在金属载体周围形成电介质层之前通过金属载体形成通孔，其中介电层的形成包括在通孔内形成电介质层。

公开(公告)号：US06277799B1

公开(公告)日：2001-08-21

申请号：US09344886

申请日：1999-06-25

申请人： Krishna G. Sachdev ,  James N. Humenik ,  John U. Knickerbocker ,  Glenn A. Pomerantz

发明人： Krishna G. Sachdev ,  James N. Humenik ,  John U. Knickerbocker ,  Glenn A. Pomerantz

IPC分类号： C11D172

CPC分类号： C11D11/0047 ,  C11D1/008 ,  C11D1/02 ,  C11D1/24 ,  C11D1/29 ,  C11D1/66 ,  C11D1/662 ,  C11D1/72 ,  C11D1/88 ,  C11D1/90 ,  C11D3/2086 ,  H05K3/1216 ,  H05K3/26

摘要： This invention relates to an aqueous cleaning method for removal of metal-organic composite paste residue from the surface of components, such as, screening masks, associated paste screening equipment, substrates, to name a few. The invention is particularly concerned with aqueous alkaline cleaning solutions comprising alkali metal salt and/or quaternary ammonium salt of an organic acid preferably &agr;-hydroxy carboxylic acid in the presence of excess alkali and optionally a surface active agent for use in cleaning components, such as, screening masks, associated screening equipment, substrates, etc., which are used in the production of electronic components.

摘要翻译： 本发明涉及从组分表面除去金属 - 有机复合糊状残留物的水性清洗方法，例如筛选掩模，相关的糊状物筛选设备，底物等等。 本发明特别涉及含有碱金属盐和/或季铵盐的含水碱性清洗溶液，所述碱性金属盐和/或有机酸优选为α-羟基羧酸的季铵盐，所述碱性金属盐和/或季铵盐在过量碱和任选的表面活性剂存在下用于清洁组分，例如 ，筛选掩模，相关筛选设备，基材等，用于生产电子元件。

公开(公告)号：US06228682B1

公开(公告)日：2001-05-08

申请号：US09469157

申请日：1999-12-21

申请人： Mukta S. Farooq ,  John U. Knickerbocker ,  Srinivasa S. Reddy

发明人： Mukta S. Farooq ,  John U. Knickerbocker ,  Srinivasa S. Reddy

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L25/165 ,  H01L2224/13099 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30107 ,  H05K1/023 ,  H05K1/183 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00

摘要： The distance between a discrete or passive electrical component and an electrical semiconductor device and substrate or carrier is minimized by shortening the lead length connections of the passive component. One or more passive electronic components are mounted within the body of a carrier or board by creating a cavity in the substrate or carrier that is directly below a semiconductor device. The passive component is electrically connected to the substrate and device using solder bump technology resulting in much shorter lead length connections to and from the passive component.