公开(公告)号：US06193576B1

公开(公告)日：2001-02-27

申请号：US09082287

申请日：1998-05-19

申请人： Michael A. Gaynes ,  Allan O. Johnson ,  Ramesh R. Kodnani ,  Mark V. Pierson ,  Edward J. Tasillo

发明人： Michael A. Gaynes ,  Allan O. Johnson ,  Ramesh R. Kodnani ,  Mark V. Pierson ,  Edward J. Tasillo

IPC分类号： H01J900

CPC分类号： G02F1/13336 ,  Y10S345/903

摘要： A method for aligning a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate is arranged on a coverplate support. A first layer of a bonding material is applied to at least one of a first side of each of the tiles and a surface of the coverplate on which the tiles are to be secured. The tiles are arranged on the coverplate, such that the first layer of bonding material is arranged between the tiles and the coverplate. The tiles are connected to an alignment apparatus. The tiles are aligned relative to each other and the coverplate. The tiles are at least partially secured to the coverplate.

摘要翻译： 一种用于对准多个用于构建平板显示器的薄膜晶体管瓦片的方法。 盖板安装在盖板支架上。 接合材料的第一层被施加到每个瓷砖的第一侧中的至少一个以及待固定瓷砖的盖板的表面。 瓦片布置在盖板上，使得第一层粘合材料布置在瓦片和盖板之间。 瓦片连接到对准装置。 瓷砖相对于彼此和盖板对准。 瓦片至少部分地固定到盖板上。

公开(公告)号：US06177729B1

公开(公告)日：2001-01-23

申请号：US09303290

申请日：1999-04-03

申请人： Joseph A. Benenati ,  Claude L. Bertin ,  William T. Chen ,  Thomas E. Dinan ,  Wayne F. Ellis ,  Wayne J. Howell ,  John U. Knickerbocker ,  Mark V. Pierson ,  William R. Tonti ,  Jerzy M. Zalesinski

发明人： Joseph A. Benenati ,  Claude L. Bertin ,  William T. Chen ,  Thomas E. Dinan ,  Wayne F. Ellis ,  Wayne J. Howell ,  John U. Knickerbocker ,  Mark V. Pierson ,  William R. Tonti ,  Jerzy M. Zalesinski

IPC分类号： H01L2348

CPC分类号： H01L24/16 ,  G01R1/0483 ,  H01L24/11 ,  H01L24/12 ,  H01L24/17 ,  H01L24/83 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2224/17051 ,  H01L2224/2919 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/111 ,  H05K3/321 ,  H05K2201/0133 ,  H05K2201/0212 ,  H05K2201/0221 ,  H05K2201/0233 ,  H05K2201/10234 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/0307 ,  Y10T428/12472 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014

摘要： An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.

摘要翻译： 集成电路组件具有与滚动金属球电连接到衬底的焊盘的芯片焊盘。 柔韧的材料将球与芯片和衬底的焊盘可动地接触。 由于球相对自由移动，因此在现有技术的连接接头中通常会引起巨大应力的热膨胀差异简单地导致本发明的滚珠滚动，从而完全避免热应力。 与C4焊料凸块相比，连接的可靠性大大提高，尽管存在大量的热失配，芯片可以安全地直接安装到诸如PC板的基板上。

公开(公告)号：US6142361A

公开(公告)日：2000-11-07

申请号：US458483

申请日：1999-12-09

申请人： Francis J. Downes, Jr. ,  Robert M. Japp ,  Mark V. Pierson

发明人： Francis J. Downes, Jr. ,  Robert M. Japp ,  Mark V. Pierson

IPC分类号： H01L21/60 ,  H05K3/30 ,  H05K3/34 ,  B23K1/20 ,  B23K31/02

CPC分类号： H01L24/81 ,  B23K2201/40 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  Y10T29/4913 ,  Y10T29/53196

摘要： A method, and associated structure, for adhesively coupling a chip to an organic chip carrier. The chip is attached to a top surface of the organic chip carrier by interfacing a solder bump between a C4 solder structure on the chip and a pad on a top surface of the chip carrier. The melting temperature of the solder bump is less than the melting temperature of the C4 solder structure. A block of ferrous material is placed on a top surface of the chip. A temporary or permanent stiffener of ferrous material is placed on the top surface of the chip carrier. A permanent magnet is coupled to a bottom surface of the chip carrier. Alternatively, an electromagnetic could be utilized instead of the electromagnet. Due to the permanent magnet or the electromagnet, a magnetic force on the stiffener is directed toward the magnet and substantially flattens the first surface of the chip carrier. Similarly, a magnetic force on the block is directed toward the magnet such that the electronic component and the chip carrier are held in alignment. The solder bump is reflowed at a temperature between the melting temperature of the solder bump and the melting temperature of the C4 solder structure. The reflowing reconfigures the solder bump. The magnetic force on the block frictionally clamps the reflowed solder between the C4 solder structure and the pad. The chip and carrier are cooled, resulting in the C4 solder structure being adhesively and conductively coupled to the pad.

摘要翻译： 一种用于将芯片粘合地耦合到有机芯片载体的方法和相关联的结构。 芯片通过在芯片上的C4焊料结构和芯片载体的顶表面上的焊盘之间接合焊料凸块来附接到有机芯片载体的顶表面。 焊料凸点的熔化温度小于C4焊料结构的熔化温度。 将一块黑色金属材料放置在芯片的上表面上。 铁芯材料的临时或永久性加强件被放置在芯片载体的顶表面上。 永磁体耦合到芯片载体的底表面。 或者，可以使用电磁来代替电磁体。 由于永磁体或电磁体，加强件上的磁力被引向磁体并且基本平坦化芯片载体的第一表面。 类似地，块上的磁力指向磁体，使得电子部件和芯片载体保持对准。 在焊料凸块的熔化温度和C4焊料结构的熔化温度之间的温度下回流焊料凸点。 回流重新配置焊料凸块。 块上的磁力摩擦地夹住C4焊料结构和焊盘之间的回流焊料。 芯片和载体被冷却，导致C4焊料结构被粘性地导电耦合到焊盘。

公开(公告)号：US6100114A

公开(公告)日：2000-08-08

申请号：US132127

申请日：1998-08-10

申请人： Cynthia S. Milkovich ,  Mark V. Pierson ,  Son K. Tran

发明人： Cynthia S. Milkovich ,  Mark V. Pierson ,  Son K. Tran

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/11 ,  H01L21/563 ,  H01L24/29 ,  H01L24/31 ,  H01L24/94 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/83951 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14

摘要： Solder bumps on electronic components are encapsulated before attachment to a substrate or component carrier. A film of sealing material is pressed against top portions of the solder bumps by pressing with a layer of low durometer flexible material. Encapsulant is positioned between the component and the film and in contact with the bumps, and partially cured. The film and layer of flexible material are removed to expose the top portions of the encapsulated solder bumps.

摘要翻译： 电子元件下的焊料凸点在附着到基板或部件载体之前被封装。 通过用低硬度柔性材料层压制，将密封材料膜压在焊料凸块的顶部上。 封装剂位于组件和膜之间并与凸块接触并部分固化。 去除柔性材料的膜和层以暴露封装的焊料凸块的顶部。

公开(公告)号：US6068175A

公开(公告)日：2000-05-30

申请号：US162739

申请日：1998-09-29

申请人： Craig G. Heim ,  Russell H. Lewis ,  Mark V. Pierson ,  Karl J. Puttlitz

发明人： Craig G. Heim ,  Russell H. Lewis ,  Mark V. Pierson ,  Karl J. Puttlitz

IPC分类号： B23K1/012 ,  B23K3/08 ,  C08G61/00 ,  C08G63/91 ,  C08L63/00 ,  C08L67/02 ,  C08L71/12 ,  H05K3/34 ,  B23K37/02 ,  B23K1/00 ,  B23K5/00 ,  B23K31/00 ,  B23K31/02

CPC分类号： H05K3/3494 ,  B23K1/012 ,  B23K3/08 ,  C08G61/00 ,  C08G63/914 ,  C08L63/00 ,  C08L67/02 ,  C08L71/126 ,  H01L24/75 ,  H05K3/3415 ,  B23K2201/40 ,  B23K2201/42 ,  H01L2224/16225 ,  H05K2201/10734 ,  H05K2203/0173 ,  H05K2203/081 ,  H05K2203/1105 ,  H05K2203/1572 ,  H05K2203/176 ,  H05K3/3436 ,  Y02P70/613 ,  Y10S29/024 ,  Y10S29/044 ,  Y10T29/49144 ,  Y10T29/53191 ,  Y10T29/53265

摘要： Apparatus for connecting a first area array component to a substrate with a joining material. The apparatus has a nozzle directing heat toward both the first area array component and the portion of the substrate beneath the first area array component to melt the joining material. An elastic seal contacts the substrate and prevents the heat from affecting other components adjacent the first area array component. The nozzle is pressed against the substrate to restrain warping of the substrate, which might be caused by the heating of the first area array component, and to prevent damage to the substrate. The nozzle can tilt so that it conforms to the surface of the substrate. The first area array component is allowed to move freely in the direction of a plane of the substrate under the surface tension of the molten joining material during heating to center the first area array component.

摘要翻译： 用于使用接合材料将第一区域阵列部件连接到基板的装置。 该装置具有将第一区域阵列部件和第一区域阵列部件下方的基板部分朝着第二区域阵列部件的两个热导向的喷嘴，以熔化接合材料。 弹性密封件接触基板并防止热量影响与第一区域阵列部件相邻的其他部件。 喷嘴被压靠在基板上以抑制基板的翘曲，这可能是由第一区域阵列部件的加热引起的，并且防止损坏基板。 喷嘴可以倾斜使其符合基板的表面。 允许第一区域阵列部件在加热期间在熔融接合材料的表面张力下在基板的平面方向上自由移动以使第一区域阵列部件居中。

公开(公告)号：US5889654A

公开(公告)日：1999-03-30

申请号：US826963

申请日：1997-04-09

申请人： Mark V. Pierson ,  Kenneth L. Spink, Jr. ,  Thurston B. Youngs, Jr.

发明人： Mark V. Pierson ,  Kenneth L. Spink, Jr. ,  Thurston B. Youngs, Jr.

IPC分类号： B42D15/10 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K5/02 ,  H05K7/20

CPC分类号： H05K5/0269 ,  H01L23/5388 ,  H05K7/20445 ,  H01L2224/48472 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14

摘要： Integrated circuit chips (18, 42, or 56) are packaged within openings formed in a substrate such as PCMCIA Card (20, 40, or 54), thus allowing compliance with overall width dimension requirements for standardized electronic components. The arrangement has the advantages that thermal coefficient of expansion of the chips and cards match, and that a sturdy, multilayer ceramic substrate is used for electrical connection to electronic devices such as laptops, palmtops, and the like. In addition, a second integrated circuit chip (68) can be connected directly to the embedded chip (56), thereby allowing two chips to be accommodated in a card (54) at the same location and allowing chip-to-chip electrical communication. A variety of electrical bonding methods joining the embedded chip to the card can be employed. In addition, a variety of thermal conduction arrangements can be used for cooling the embedded integrated circuit chip.

摘要翻译： 集成电路芯片（18,42或56）封装在诸如PCMCIA卡（20,40或54）的基板中形成的开口内，从而允许符合标准化电子元件的整体宽度尺寸要求。 该布置具有芯片和卡的热膨胀系数匹配的优点，并且使用坚固的多层陶瓷基板来电连接到诸如笔记本电脑，掌上电脑等的电子设备。 此外，第二集成电路芯片（68）可以直接连接到嵌入式芯片（56），从而允许两个芯片被容纳在相同位置的卡（54）中，并允许芯片间的电气通信。 可以采用将嵌入式芯片连接到卡的各种电接合方法。 此外，可以使用各种热传导布置来冷却嵌入式集成电路芯片。

公开(公告)号：US5523696A

公开(公告)日：1996-06-04

申请号：US163452

申请日：1993-12-07

申请人： Richard G. Charlton ,  George C. Correla ,  Mark A. Couture ,  Gary R. Hill ,  Kibby B. Horsford ,  Anthony P. Ingraham ,  Michael D. Lowell ,  Voya R. Markovich ,  Gordon C. Osborne, Jr. ,  Mark V. Pierson

发明人： Richard G. Charlton ,  George C. Correla ,  Mark A. Couture ,  Gary R. Hill ,  Kibby B. Horsford ,  Anthony P. Ingraham ,  Michael D. Lowell ,  Voya R. Markovich ,  Gordon C. Osborne, Jr. ,  Mark V. Pierson

IPC分类号： G01R1/04 ,  G01R1/073 ,  G01R31/28

CPC分类号： G01R31/2863 ,  G01R1/0483 ,  G01R1/07307 ,  G01R31/2886

摘要： A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

摘要翻译： 公开了一种用于测试半导体芯片的方法和装置。 单个半导体芯片具有I / O触点。 该装置设置有具有对应于半导体芯片上的触点的触点的插入器。 芯片和内插器触点都可以是任何已知的类型，包括金属球，凸块或凸片，或者可以设置有树枝状表面。 首先将芯片触点与插入件上的触点进行相对松动的临时接触，然后将大于每芯片接触5克的压缩力施加到芯片上以迫使芯片触头与插入器触点良好地电接触。 然后进行芯片的测试。 测试可能包括加热芯片以及将信号应用于芯片触点。 测试后，芯片从基板上取下。

公开(公告)号：US5290992A

公开(公告)日：1994-03-01

申请号：US957969

申请日：1992-10-07

申请人： How T. Lin ,  Mark V. Pierson

发明人： How T. Lin ,  Mark V. Pierson

IPC分类号： B23K26/06 ,  B23K26/067 ,  G03F7/20

CPC分类号： B23K26/0673 ,  B23K26/066 ,  B23K26/067 ,  G03F7/2002 ,  G03F7/70291 ,  G03F7/70991

摘要： The present invention is an apparatus and method for maximizing light beam utilization in patterning applications by positioning a plurality of mask mirrors in the light beam path to form patterned light onto a plurality of work pieces. Each mask mirror is designed so that a portion of the light beam area needed for exposing a work piece to patterned light is reflected from the mask mirror, while the remainder is passed through the mask mirror to another mask mirror. Alternatively, each mask mirror can be designed so that a portion of the light beam area needed for exposing a work piece to patterned light is passed through the mask mirror, while the remainder is reflected to another mask mirror.

摘要翻译： 本发明是一种用于通过在光束路径中定位多个掩模反射镜以在多个工件上形成图案化光来最大化图案化应用中的光束利用的装置和方法。 每个掩模镜被设计成使得用于将工件暴露于图案化光所需的光束区域的一部分从掩模反射镜反射，而其余部分通过掩模镜到另一个掩模反射镜。 或者，每个掩模反射镜可被设计成使得将工件暴露于图案化光所需的光束区域的一部分通过掩模反射镜，而剩余部分被反射到另一个掩模反射镜。

公开(公告)号：US4741100A

公开(公告)日：1988-05-03

申请号：US911186

申请日：1986-09-24

申请人： Mark V. Pierson

发明人： Mark V. Pierson

IPC分类号： H01R12/04 ,  B21K25/00 ,  H01L21/48 ,  H01R43/04 ,  H01R43/20 ,  H05K3/30 ,  H01R9/16 ,  B23P19/00

CPC分类号： H01R43/20 ,  B21K25/00 ,  H01L21/4853 ,  H05K3/308 ,  Y10T29/49153 ,  Y10T29/53174

摘要： A pin which has a compressive strength less than the tensile strength of a substrate can be fixed into a hole in the substrate when the substrate is held between a stopping block and a clamp by transporting the pin into the hole with sufficient kinetic energy that the pin is forged into a shape defined by the hole upon impacting the stopping block.The pin can be retained in the substrate by forging it into a headed and bulged shape defined by recesses in the stopping block and the clamp on either side of the hole.

公开(公告)号：US4422232A

公开(公告)日：1983-12-27

申请号：US203562

申请日：1980-11-05

申请人： Stanley R. Vancelette ,  Robert D. DiNozzi ,  Mark V. Pierson

发明人： Stanley R. Vancelette ,  Robert D. DiNozzi ,  Mark V. Pierson

IPC分类号： B23P21/00 ,  H05K13/00 ,  H05K13/04 ,  H05K3/30

CPC分类号： H05K13/0452 ,  Y10T29/49139 ,  Y10T29/5138 ,  Y10T29/53183 ,  Y10T29/53261

摘要： An insertion device for two or four pin dual in-line electronic insertion machines which include a radial array of transfer units associated with a picker unit which grasps a component and inserts it into a circuit board.

摘要翻译： 一种用于两针或四针双列直插式电子插入机的插入装置，其包括与抓取部件并将其插入电路板中的拾取器单元相关联的传送单元的径向阵列。