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    Semiconductor device and semiconductor system including the same
    31.
    发明授权
    Semiconductor device and semiconductor system including the same 有权
    半导体器件和包括其的半导体系统

    公开(公告)号：US09042192B2

    公开(公告)日：2015-05-26

    申请号：US13602077

    申请日：2012-08-31

    申请人： Byung Deuk Jeon

    发明人： Byung Deuk Jeon

    IPC分类号： G11C7/00 ,  G11C8/12 ,  G11C29/12 ,  G11C29/26 ,  G11C11/40

    CPC分类号： G11C29/00 ,  G11C7/1057 ,  G11C8/12 ,  G11C11/40 ,  G11C29/1201 ,  G11C29/26 ,  G11C2029/2602

    摘要： A semiconductor device includes two or more memory chips electrically coupled. Each of the memory chips includes global lines, a MUX unit, a selection unit, and an output unit. The global lines transmit data stored in memory cells. The MUX unit receives the data loaded onto the global lines to output a test data. The selection unit is inserted into two or more of the global lines and configured to output the test data instead of the data loaded onto the two or more global lines, in a test mode. The output unit is coupled to the global lines and is configured to output the data in a normal mode, and output the test data received from any one of the two or more global lines connected to the selection unit to an I/O pad based on information about the memory chip in a test mode.

    摘要翻译： 半导体器件包括电耦合的两个或更多个存储器芯片。 每个存储器芯片包括全局线，MUX单元，选择单元和输出单元。 全局线传输存储在存储单元中的数据。 MUX单元接收加载到全局线上的数据以输出测试数据。 选择单元被插入到两条或多条全局线中，并配置成在测试模式下输出测试数据而不是加载到两条或多条全局线上的数据。 输出单元耦合到全局线路，并且被配置为以正常模式输出数据，并且将从连接到选择单元的两个或更多个全局线路中的任一个接收的测试数据输出到基于 在测试模式下有关内存芯片的信息。

    MEMORY SYSTEMS AND METHODS OF MANAGING FAILED MEMORY CELLS OF SEMICONDUCTOR MEMORIES
    32.
    发明申请
    MEMORY SYSTEMS AND METHODS OF MANAGING FAILED MEMORY CELLS OF SEMICONDUCTOR MEMORIES 有权
    存储器系统和管理半导体存储器故障存储器单元的方法

    公开(公告)号：US20150143165A1

    公开(公告)日：2015-05-21

    申请号：US14326966

    申请日：2014-07-09

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sangyeun CHO

    IPC分类号： G06F11/10

    CPC分类号： G11C29/50016 ,  G06F12/126 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/1044 ,  G11C7/1009 ,  G11C11/40 ,  G11C29/76

    摘要： A memory system includes a memory controller configured to replace a memory block including a failed memory cell with a unit cache block of a cache memory in response to detection of the failed memory cell in the memory block. The unit cache block is smaller than a minimum size of a memory cell array capable of being blocked by an operating system, and the unit cache block has substantially the same storage capacity as the memory block.

    摘要翻译： 存储器系统包括存储器控制器，其被配置为响应于检测到存储器块中的故障存储器单元而将包括故障存储器单元的存储器块与高速缓冲存储器的单元高速缓存块替换。 单元高速缓存块小于能够被操作系统阻塞的存储单元阵列的最小尺寸，并且单元高速缓存块具有与存储块大致相同的存储容量。

    SEMICONDUCTOR DEVICES INCLUDING VERTICAL MEMORY CELLS AND METHODS OF FORMING SAME
    33.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING VERTICAL MEMORY CELLS AND METHODS OF FORMING SAME 有权
    包括垂直存储器单元的半导体器件及其形成方法

    公开(公告)号：US20150129955A1

    公开(公告)日：2015-05-14

    申请号：US14075480

    申请日：2013-11-08

    申请人： Micron Technology, Inc.

    发明人： Wolfgang Mueller ,  Sanh D. Tang ,  Sourabh Dhir ,  Srinivas Pulugurtha

    IPC分类号： H01L29/78 ,  H01L27/105 ,  H01L29/66

    CPC分类号： H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

    摘要： A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed.

    摘要翻译： 半导体器件可以包括存储器阵列，其包括连接到数字线，字线和主体连接线的垂直存储器单元。 存储器阵列的行或列可以包括连接到主体连接线的一个或多个支柱。 可以通过连接到主体连接线的至少一个支柱将电压施加到主体连接线。 施加电压到身体连接线可能会减少浮体效应。 公开了形成至少一个柱和电压源之间的连接的方法。 还公开了包括这种连接的半导体器件。

    Adjustable reference voltage generator for single-ended DRAM sensing devices
    35.
    发明授权
    Adjustable reference voltage generator for single-ended DRAM sensing devices 有权
    用于单端DRAM感测器件的可调参考电压发生器

    公开(公告)号：US09000837B1

    公开(公告)日：2015-04-07

    申请号：US14072321

    申请日：2013-11-05

    申请人： International Business Machines Corporation

    发明人： John A. Fifield

    IPC分类号： G05F1/10 ,  G05F5/00

    CPC分类号： G11C29/028 ,  G11C11/40 ,  G11C29/021

    摘要： Methods, systems, and structures for generating a target reference voltage are provided. A circuit includes a voltage adjuster, a switch, and a current source. The switch selectively connects the current source to circuit paths in the voltage adjuster. A first of the circuit paths incrementally decreases the target reference voltage with respect to the input voltage. A second of the circuit paths incrementally increases the target voltage with respect to the input voltage.

    摘要翻译： 提供了用于产生目标参考电压的方法，系统和结构。 电路包括电压调节器，开关和电流源。 开关选择性地将电流源连接到电压调节器中的电路路径。 电路中的第一路径相对于输入电压递增地降低目标参考电压。 电路中的第二路径相对于输入电压递增地增加目标电压。

    Semiconductor device having a control chip stacked with a controlled chip
    36.
    发明授权
    Semiconductor device having a control chip stacked with a controlled chip 有权
    具有堆叠有受控芯片的控制芯片的半导体器件

    公开(公告)号：US08988919B2

    公开(公告)日：2015-03-24

    申请号：US14274267

    申请日：2014-05-09

    申请人： PS4 Luxco S.a.r.l.

    发明人： Yoshiro Riho

    IPC分类号： G11C5/06 ,  G11C7/22 ,  G11C7/10 ,  G11C7/06 ,  G11C11/4063 ,  H03L7/097 ,  G11C29/02 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  H03L7/081 ,  G11C11/40 ,  H01L25/065

    CPC分类号： G11C11/4063 ,  G11C5/063 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/40 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2924/1305 ,  H01L2924/13091 ,  H03L7/0812 ,  H03L7/097 ,  H01L2924/00

    摘要： A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal. The control chip includes a first control circuit outputting a synchronization signal and receiving a data signal, a delay adjustment circuit delaying the synchronization signal and outputting the same as a delayed synchronization signal, a phase comparator circuit comparing the phases of the replica signal and the synchronization signal, and a delay control circuit controlling the delay amount of the delay adjustment circuit based on a comparison result of the phase comparator circuit.

    摘要翻译： 半导体器件包括第一受控芯片和与其堆叠的控制芯片。 第一受控芯片包括响应于同步信号输出数据信号的第一电路，与延迟同步信号同步地将数据信号输出到数据端的输入/输出电路，复制输出电路并输出 与延迟的同步信号同步的第一副本终端的复制信号。 控制芯片包括输出同步信号并接收数据信号的第一控制电路，延迟同步信号并将其作为延迟同步信号输出的延迟调整电路，比较复制信号和同步的相位的相位比较器电路 信号，以及延迟控制电路，其基于相位比较器电路的比较结果来控制延迟调整电路的延迟量。

    SEMICONDUCTOR STORAGE DEVICE
    37.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权
    半导体存储设备

    公开(公告)号：US20150049535A1

    公开(公告)日：2015-02-19

    申请号：US14388436

    申请日：2013-02-27

    申请人： Sharp Kabushiki Kaisha

    发明人： Yoshimitsu Yamauchi

    IPC分类号： G11C5/02 ,  G11C11/40 ,  G11C11/24

    CPC分类号： G11C5/02 ,  G11C11/24 ,  G11C11/40 ,  G11C11/405 ,  G11C14/0009 ,  H01L27/115 ,  H01L27/1156 ,  H01L27/1225

    摘要： Provided is a semiconductor storage device with which it is possible to write information to individual memory cells in which a storage node is configured with an oxide semiconductor insulated-gate FET source and a terminal of a capacitor element being connected. A storage node is configured by connecting a source of a first transistor to one terminal of a capacitor element. A drain of the first transistor and a source of a second transistor are connected to each other. A drain of the second transistor is a data input terminal. A first control terminal, which is formed by a gate of the first transistor being connected to another terminal of the capacitor element, is connected to a wordline, which extends in the row direction. A second control terminal, which is formed of a gate of the second transistor terminal, is connected to a write control line, which extends in the column direction. The storage node is connected to a gate of a third transistor, and a current flowing between a drain and a source of the third transistor is controlled according to a voltage level of the storage node.

    摘要翻译： 提供了一种半导体存储装置，其可以向存储节点配置有氧化物半导体绝缘栅FET FET和连接的电容器元件的端子的各个存储单元写入信息。 通过将第一晶体管的源极连接到电容器元件的一个端子来配置存储节点。 第一晶体管的漏极和第二晶体管的源极彼此连接。 第二晶体管的漏极是数据输入端子。 由连接到电容器元件的另一个端子的第一晶体管的栅极形成的第一控制端子连接到沿行方向延伸的字线。 由第二晶体管端子的栅极形成的第二控制端子连接到在列方向上延伸的写入控制线。 存储节点连接到第三晶体管的栅极，并且根据存储节点的电压电平来控制在第三晶体管的漏极和源极之间流动的电流。

    MEMORY CIRCUIT
    39.
    发明申请
    MEMORY CIRCUIT 有权
    存储器电路

    公开(公告)号：US20150016179A1

    公开(公告)日：2015-01-15

    申请号：US14333582

    申请日：2014-07-17

    申请人： Semiconductor Energy Laboratory Co., Ltd.

    发明人： Masashi Fujita

    IPC分类号： G11C11/40 ,  G11C14/00 ,  H01L29/786

    CPC分类号： G11C11/40 ,  G11C5/005 ,  G11C5/06 ,  G11C7/00 ,  G11C7/20 ,  G11C11/34 ,  G11C14/00 ,  G11C14/0009 ,  G11C14/0054 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/792

    摘要： While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit.

    摘要翻译： 在电源供应停止的情况下，可以将保持在易失性存储部中的数据信号保持在非易失性存储部。 在非易失性存储器部分中，具有极低截止电流的晶体管允许数据信号长时间保持在电容器中。 因此，即使在停止供电时，非易失性存储部也能够保持逻辑状态。 当再次开始供电时，在电源供应停止时保持在电容器中的数据信号被设定为通过接通复位电路而不发生故障的电位。

    Complementary SOI lateral bipolar for SRAM in a CMOS platform
    40.
    发明授权
    Complementary SOI lateral bipolar for SRAM in a CMOS platform 有权
    CMOS平台中SRAM的互补SOI横向双极性

    公开(公告)号：US08917547B2

    公开(公告)日：2014-12-23

    申请号：US13954206

    申请日：2013-07-30

    申请人： International Business Machines Corporation

    发明人： Jin Cai ,  Leland Chang ,  Jeffrey W. Sleight

    IPC分类号： G11C11/34 ,  H01L21/8232 ,  G11C11/40 ,  H01L27/12

    CPC分类号： G11C11/40 ,  G11C11/411 ,  H01L21/8232 ,  H01L27/1203

    摘要： A memory array that includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage.

    摘要翻译： 包括在SOI衬底上制造的SOI衬底和横向双极结型晶体管（BJT）的存储器阵列。 BJT形成第一和第二反相器交叉耦合以形成存储单元。 读出电路输出存储单元的二进制状态。 电源被配置为向读取电路提供Vdd电压，并将Vcc和Vee电压提供给第一组横向双极晶体管和第二组横向双极晶体管，其中Vee电压至少为零伏， Vcc电压大于Vee电压并且等于或小于Vdd电压。