公开(公告)号：US10141449B2

公开(公告)日：2018-11-27

申请号：US15037610

申请日：2015-09-15

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Meili Wang ,  Hongda Sun ,  Fengjuan Liu ,  Lungpao Hsin

IPC分类号： H01L29/786 ,  H01L29/10 ,  H01L29/225 ,  H01L29/227 ,  H01L29/24 ,  H01L27/12

摘要： The embodiments of the present invention provides an oxide TFT, an array substrate and a display device, an oxide channel layer of the oxide TFT comprises a front channel oxide layer and a back channel oxide layer, a conduction band bottom of the back channel oxide layer being higher than a conduction band bottom of the front channel oxide layer, and a band gap of the back channel oxide layer being larger than a band gap of the front channel oxide layer. In the oxide TFT, the array substrate and the display device provided in the present invention, it is possible to accumulate a large number of electrons through the potential difference formed between oxide channel layers of a multilayer structure so as to increase the carrier concentration in the oxide channel layers to achieve the purpose of improving TFT mobility without damaging TFT stability.

公开(公告)号：US20180211897A1

公开(公告)日：2018-07-26

申请号：US15597386

申请日：2017-05-17

申请人： QUALCOMM Incorporated

发明人： Bin YANG ,  Gengming TAO ,  Xia LI

IPC分类号： H01L23/367 ,  H01L29/737 ,  H01L29/205 ,  H01L29/225 ,  H01L29/66

CPC分类号： H01L29/66969 ,  H01L23/3677 ,  H01L29/0821 ,  H01L29/205 ,  H01L29/225 ,  H01L29/41708 ,  H01L29/66318 ,  H01L29/7371

摘要： A heterojunction bipolar transistor may include an emitter, a base contacting the emitter, a collector contacting the base, a sub-collector contacting the collector, and an electrical isolation layer contacting the sub-collector. The heterojunction bipolar transistor may also include a backside heatsink thermally coupled to the sub-collector and the collector. The backside heatsink may be aligned with a central axis of the emitter and the base.

公开(公告)号：US09772301B2

公开(公告)日：2017-09-26

申请号：US14611882

申请日：2015-02-02

申请人： INHA-INDUSTRY PARTNERSHIP INSTITUTE

发明人： Sang Sub Kim ,  Sun-Woo Choi ,  Akash Katoch

IPC分类号： G01N27/414 ,  H01L29/06 ,  H01L29/225 ,  H01L21/02 ,  B82Y15/00 ,  B82Y40/00 ,  H01L29/24 ,  G01N27/12

CPC分类号： G01N27/4146 ,  B82Y15/00 ,  B82Y40/00 ,  G01N27/127 ,  H01L21/02554 ,  H01L21/02603 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/225 ,  H01L29/24

摘要： The present invention relates to a sensor including a core-shell nanostructure, and more particularly, to a sensor including: a base material; a sensing part including a core-shell nanostructure that has a core including a first metal oxide and a shell including a second metal oxide formed on the core; and two electrode layers spaced from each other on the sensing part.

公开(公告)号：US09490363B2

公开(公告)日：2016-11-08

申请号：US14782284

申请日：2014-03-31

申请人： PEKING UNIVERSITY

发明人： Ru Huang ,  Qianqian Huang ,  Chunlei Wu ,  Jiaxin Wang ,  Yangyuan Wang

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/739 ,  H01L21/02 ,  H01L21/027 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/06 ,  H01L29/10 ,  H01L29/267 ,  H01L29/165 ,  H01L29/205 ,  H01L29/225 ,  H01L21/28

CPC分类号： H01L29/7835 ,  H01L21/02636 ,  H01L21/0274 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28238 ,  H01L21/308 ,  H01L21/32139 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/205 ,  H01L29/225 ,  H01L29/267 ,  H01L29/66356 ,  H01L29/66659 ,  H01L29/66977 ,  H01L29/7391

摘要： The present invention discloses a tunneling field effect transistor having a three-side source and a fabrication method thereof, referring to field effect transistor logic devices and circuits in CMOS ultra large scale integrated circuits (ULSI). By means of the strong depletion effect of the three-side source, the transistor can equivalently achieve a steep doping concentration gradient for the source junction, significantly optimizing the sub-threshold slope of the TFET. Meanwhile, the turn-on current of the transistor is boosted. Furthermore, due to a region uncovered by the gate between the gate and the drain, the bipolar conduction effect of the transistor is effectively inhibited, and on the other hand, in the small-size transistor a parasitic tunneling current at the corner of the source junction is inhibited. The fabrication method is simple and can be accurately controlled. By forming the channel region using an epitaxy method subsequent to etching, it facilitates to form a steeper doping concentration gradient for the source region or form a hetero-junction. Moreover, the fabrication flow of the post-gate process facilitates to integrate a high-k gate dielectric/a metal gate having good quality, further improving the performance of the transistor.

摘要翻译： 本发明公开了一种具有三面源的隧道场效应晶体管及其制造方法，参考CMOS超大规模集成电路（ULSI）中的场效应晶体管逻辑器件和电路。 通过三侧源的强消耗效应，晶体管可以等效地实现源极结的陡峭掺杂浓度梯度，显着优化了TFET的次阈值斜率。 同时，提高了晶体管的导通电流。 此外，由于栅极和漏极之间的栅极未覆盖的区域，晶体管的双极导电效应被有效地抑制，另一方面，在小尺寸晶体管中，源极的角落处的寄生隧穿电流 结被抑制。 制作方法简单，可以精确控制。 通过在蚀刻之后使用外延法形成沟道区，有助于形成源区的更陡的掺杂浓度梯度或形成异质结。 此外，栅极后工艺的制造流程有助于集成具有良好质量的高k栅极电介质/金属栅极，进一步提高晶体管的性能。

公开(公告)号：US20150364645A1

公开(公告)日：2015-12-17

申请号：US14599181

申请日：2015-01-16

申请人： Rohm and Haas Electronic Materials, LLC

发明人： Moonsub Shim ,  Nuri Oh ,  You Zhai ,  Sooji Nam ,  Peter Trefonas ,  Kishori Deshpande ,  Jake Joo

IPC分类号： H01L33/06 ,  H01L21/02 ,  H01L29/12 ,  H01L31/18 ,  H01L31/0296 ,  H01L31/0352 ,  H01L33/28 ,  H01L33/00 ,  H01L29/06 ,  H01L29/225

CPC分类号： H01L33/06 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02601 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/02628 ,  H01L29/0669 ,  H01L29/068 ,  H01L29/125 ,  H01L29/127 ,  H01L29/225 ,  H01L31/0296 ,  H01L31/035218 ,  H01L31/035227 ,  H01L31/1828 ,  H01L33/0083 ,  H01L33/18 ,  H01L33/28 ,  H01L33/502 ,  H01L51/0037 ,  H01L51/0042 ,  H01L51/502 ,  H01L51/5072 ,  H01L2251/5369 ,  Y10S977/762 ,  Y10S977/825 ,  Y10S977/949

摘要： Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.

摘要翻译： 本文公开了包含具有第一端和第二端的一维半导体纳米颗粒的半导体纳米颗粒; 第二端与第一端相反; 和两个第一端盖，其中一个端接触第一端，另一端接触一维半导体纳米颗粒的第二端; 其中与第一端接触的第一端帽包括第一半导体，并且其中第一端帽从一维半导体纳米颗粒的第一端延伸以形成第一纳米晶体异质结; 其中与第二端接触的第一端盖包括第二半导体; 其中第一端帽从一维半导体纳米颗粒的第二端延伸以形成第二纳米晶体异质结; 并且其中第一半导体和第二半导体在化学上彼此不同。

公开(公告)号：US20150300980A1

公开(公告)日：2015-10-22

申请号：US14611882

申请日：2015-02-02

申请人： INHA-INDUSTRY PARTNERSHIP INSTITUTE

发明人： Sang Sub KIM ,  Sun-Woo CHOI ,  Akash KATOCH

IPC分类号： G01N27/414 ,  H01L29/06 ,  H01L29/225

CPC分类号： G01N27/4146 ,  B82Y15/00 ,  B82Y40/00 ,  G01N27/127 ,  H01L21/02554 ,  H01L21/02603 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/225 ,  H01L29/24

摘要： The present invention relates to a sensor including a core-shell nanostructure, and more particularly, to a sensor including: a base material; a sensing part including a core-shell nanostructure that has a core including a first metal oxide and a shell including a second metal oxide formed on the core; and two electrode layers spaced from each other on the sensing part.

摘要翻译： 本发明涉及一种包括核 - 壳纳米结构的传感器，更具体地涉及一种传感器，包括：基材; 感测部分，包括具有包括第一金属氧化物的芯和包含形成在芯上的第二金属氧化物的壳的核 - 壳纳米结构; 以及在感测部分上彼此间隔开的两个电极层。

公开(公告)号：US20150014629A1

公开(公告)日：2015-01-15

申请号：US14284228

申请日：2014-05-21

申请人： QD VISION, INC.

发明人： CRAIG BREEN ,  WENHAO LIU

IPC分类号： H01L29/15 ,  H01L21/02 ,  H01L29/225

CPC分类号： H01L29/151 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  C09K11/02 ,  C09K11/883 ,  H01L21/02409 ,  H01L21/02521 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02601 ,  H01L21/02628 ,  H01L29/0665 ,  H01L29/127 ,  H01L29/20 ,  H01L29/225 ,  Y10S977/774 ,  Y10S977/892 ,  Y10S977/95

摘要： A coated quantum dot and methods of making coated quantum dots are provided.

摘要翻译： 提供涂覆量子点和制备涂覆量子点的方法。

公开(公告)号：US08927984B2

公开(公告)日：2015-01-06

申请号：US13743062

申请日：2013-01-16

申请人： RamGoss, Inc.

发明人： Bunmi T. Adekore ,  James Fiorenza

IPC分类号： H01L29/12 ,  H01L29/778 ,  H01L29/66 ,  H01L27/06 ,  H01L27/085 ,  H01L29/20 ,  H01L29/06 ,  H01L29/225

CPC分类号： H01L27/0883 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/12 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/225 ,  H01L29/24 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789

摘要： A transistor device, such as a rotated channel metal oxide/insulator field effect transistor (RC-MO(I)SFET), includes a substrate including a non-polar or semi-polar wide band gap substrate material such as an Al2O3 or a ZnO or a Group-III Nitride-based material, and a first structure disposed on a first side of the substrate comprising of AlInGaN-based and/or ZnMgO based semiconducting materials. The first structure further includes an intentional current-conducting sidewall channel or facet whereupon additional semiconductor layers, dielectric layers and electrode layers are disposed and upon which the field effect of the dielectric and electrode layers occurs thus allowing for a high density monolithic integration of a multiplicity of discrete devices on a common substrate thereby enabling a higher power density than in conventional lateral power MOSFET devices.

摘要翻译： 诸如旋转的沟道金属氧化物/绝缘体场效应晶体管（RC-MO（I）SFET）的晶体管器件包括包括非极性或半极性宽带隙衬底材料如Al 2 O 3或ZnO的衬底 或基于III族氮化物的材料，以及设置在包括AlInGaN基和/或ZnMgO基半导体材料的衬底的第一侧上的第一结构。 第一结构还包括有意导电的侧壁通道或小面，因此设置了附加的半导体层，电介质层和电极层，并且在其上发生电介质层和电极层的场效应，从而允许多密度的高密度单片集成 的公共衬底上的分立器件，从而实现比常规横向功率MOSFET器件更高的功率密度。

公开(公告)号：US07863631B2

公开(公告)日：2011-01-04

申请号：US12433106

申请日：2009-04-30

申请人： Michael R. Krames ,  Nathan F. Gardner ,  Frank M. Steranka

发明人： Michael R. Krames ,  Nathan F. Gardner ,  Frank M. Steranka

IPC分类号： H01L33/00 ,  H01L29/221 ,  H01L29/225

CPC分类号： H01L33/30 ,  H01L2224/13 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

摘要： To increase the lattice constant of AlInGaP LED layers to greater than the lattice constant of GaAs for reduced temperature sensitivity, an engineered growth layer is formed over a substrate, where the growth layer has a lattice constant equal to or approximately equal to that of the desired AlInGaP layers. In one embodiment, a graded InGaAs or InGaP layer is grown over a GaAs substrate. The amount of indium is increased during growth of the layer such that the final lattice constant is equal to that of the desired AlInGaP active layer. In another embodiment, a very thin InGaP, InGaAs, or AlInGaP layer is grown on a GaAs substrate, where the InGaP, InGaAs, or AlInGaP layer is strained (compressed). The InGaP, InGaAs, or AlInGaP thin layer is then delaminated from the GaAs and relaxed, causing the lattice constant of the thin layer to increase to the lattice constant of the desired overlying AlInGaP LED layers. The LED layers are then grown over the thin InGaP, InGaAs, or AlInGaP layer.

摘要翻译： 为了将AlInGaP LED层的晶格常数提高到大于GaAs的晶格常数以降低温度敏感性，在衬底上形成工程化生长层，其中生长层具有等于或近似等于所需的晶格常数的晶格常数 AlInGaP层。 在一个实施例中，在GaAs衬底上生长渐变的InGaAs或InGaP层。 在层的生长期间铟的量增加，使得最终晶格常数等于所需的AlInGaP活性层的量。 在另一实施例中，在GaAs衬底上生长非常薄的InGaP，InGaAs或AlInGaP层，其中InGaP，InGaAs或AlInGaP层被应变（压缩）。 然后，InGaP，InGaAs或AlInGaP薄层从GaAs分层并且弛豫，导致薄层的晶格常数增加到期望的上覆AlInGaP LED层的晶格常数。 然后在薄的InGaP，InGaAs或AlInGaP层上生长LED层。

公开(公告)号：US07799664B2

公开(公告)日：2010-09-21

申请号：US11645149

申请日：2006-12-22

申请人： Peter Verheyen ,  Rita Rooyackers ,  Denis Shamiryan

发明人： Peter Verheyen ,  Rita Rooyackers ,  Denis Shamiryan

IPC分类号： H01L29/225

CPC分类号： H01L21/823814 ,  H01L29/66636 ,  Y10S438/924

摘要： One inventive aspect relates to a method of selective epitaxial growth of source/drain (S/D) areas. The method includes providing a substrate having a first and a second substrate area, the first area including at least one gate stack. The method includes applying a poly-Si or poly-SiGe top layer on the substrate, the top layer being etchable with the same etch chemistry as the substrate. The method includes removing the poly-Si or poly-SiGe top layer from the first area selectively towards the poly-Si or poly-SiGe top layer in the second area. The method includes removing simultaneously the poly-Si or poly-SiGe top layer on the second area and at least a part of the substrate in the S/D areas of the first area selectively to the gate stack. The method includes performing a selective epitaxial growth of S/D areas in the first area.

摘要翻译： 本发明的一个方面涉及源极/漏极（S / D）区域的选择性外延生长的方法。 该方法包括提供具有第一和第二衬底区域的衬底，第一区域包括至少一个栅极叠层。 该方法包括在衬底上施加多晶硅或多晶硅顶层，顶层可用与衬底相同的蚀刻化学性进行蚀刻。 该方法包括从第一区域中选择性地朝向第二区域中的多晶硅或多晶硅顶层移除多晶硅或多晶硅顶层。 该方法包括同时去除第二区域上的多晶硅或多晶硅顶层，以及在第一区域的S / D区域中的至少一部分衬底选择性地去除栅叠层。 该方法包括在第一区域中执行S / D区域的选择性外延生长。