公开(公告)号：US09460991B1

公开(公告)日：2016-10-04

申请号：US13864242

申请日：2013-04-17

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/70 ,  H01L23/62 ,  H01L23/498

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a first circuit including at least one of the first transistors, and the first circuit has a first circuit output connected to at least one of the second transistors, wherein the at least one of the second transistors is connected to a device output that is designed to be connected to external devices, and wherein the at least one of the second transistors is substantially larger than the at least one of the first transistors.

Abstract translation: 一种3D半导体器件，包括：包括第一晶体管的第一层; 覆盖所述第一晶体管并包括第二晶体管的第二层; 其中所述第二层包括直径小于150nm的贯通层通孔; 以及第一电路，其包括所述第一晶体管中的至少一个，并且所述第一电路具有连接到所述第二晶体管中的至少一个的第一电路输出，其中所述第二晶体管中的至少一个连接到设计的器件输出 以连接到外部设备，并且其中所述第二晶体管中的至少一个基本上大于所述至少一个所述第一晶体管。

公开(公告)号：US09419031B1

公开(公告)日：2016-08-16

申请号：US14461539

申请日：2014-08-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar

IPC: H01L27/146 ,  H01L21/822

CPC classification number: H01L27/14605 ,  H01L21/8221 ,  H01L25/0756 ,  H01L27/14612 ,  H01L27/14634 ,  H01L27/153 ,  H01L31/0725 ,  H01L31/1892 ,  H01L33/0079 ,  H01L33/34 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

Abstract: An integrated device, including: a first mono-crystal layer including a plurality of image sensor pixels and alignment marks; an overlaying oxide on top of the first mono-crystal layer; and a second mono-crystal layer overlaying the oxide, where the second mono-crystal layer includes a plurality of single crystal transistors aligned to the alignment marks.

Abstract translation: 一种集成装置，包括：包括多个图像传感器像素和对准标记的第一单晶层; 在第一单晶层的顶部上的覆盖氧化物; 以及覆盖所述氧化物的第二单晶层，其中所述第二单晶层包括与所述对准标记对准的多个单晶体晶体管。

公开(公告)号：US09385088B2

公开(公告)日：2016-07-05

申请号：US14626563

申请日：2015-02-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/538 ,  H01L45/00 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11 ,  H01L27/06 ,  H01L27/088 ,  H01L27/085 ,  H01L27/092 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L23/5386 ,  H01L27/0688 ,  H01L27/085 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/1108 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device including: a first layer including first transistors including at least one first monocrystalline silicon transistor channel; a second layer including second transistors including at least one second monocrystalline non-silicon transistor channel; a plurality of connection paths extending from the second transistors to the first transistors, where at least one of the connection paths includes at least one through layer via with a diameter of less than 200 nm.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一层，所述第一晶体管包括至少一个第一单晶硅晶体管沟道; 第二层，包括包括至少一个第二单晶非硅晶体管沟道的第二晶体管; 从第二晶体管延伸到第一晶体管的多个连接路径，其中至少一个连接路径包括直径小于200nm的至少一个贯穿层通孔。

公开(公告)号：US20160111369A1

公开(公告)日：2016-04-21

申请号：US14975830

申请日：2015-12-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L23/528 ,  H01L23/544 ,  H01L23/373 ,  H01L27/06

CPC classification number: H01L23/5286 ,  B82Y10/00 ,  G11C11/41 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/36 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.

Abstract translation: 一种3D IC器件，包括：包括第一单结晶晶体管的第一半导体层，其中所述第一单结晶晶体管通过至少一个包括铝或铜的金属层互连; 第二层，包括第二单结晶晶体管并且覆盖所述至少一个金属层，其中所述至少一个金属层在所述第一半导体层和所述第二层之间; 全球电力网，用于向覆盖第二层的设备分配电力; 以及局部电网以将功率分配给第一单结晶晶体管，其中全局电网通过多个通过第二层通孔连接到本地电网，并且其中通孔具有小于150nm的半径。

公开(公告)号：US09219005B2

公开(公告)日：2015-12-22

申请号：US13623756

申请日：2012-09-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Ze'ev Wurman

IPC: H01L23/48 ,  H01L21/762 ,  H01L23/544 ,  H01L21/683 ,  H01L27/06 ,  H01L27/092 ,  B82Y10/00 ,  H01L21/84 ,  H01L29/66 ,  H01L27/02 ,  H01L29/78 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  G11C16/04 ,  G11C16/10 ,  H01L29/786 ,  H01L29/10 ,  H01L23/00 ,  H01L25/065 ,  H01L27/088 ,  G11C11/41 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44

CPC classification number: B82Y10/00 ,  G11C11/41 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0655 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D IC based mobile system including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a plurality of thermal paths between the second mono-crystallized transistors and a heat removal apparatus, where at least one of the plurality of thermal paths includes a thermal contact adapted to conduct heat and not conduct electricity; and a heat spreader layer between the second layer and the at least one metal layer.

Abstract translation: 一种基于3D IC的移动系统，包括：包括第一单结晶晶体管的第一半导体层，其中第一单结晶晶体管通过包括铝或铜的至少一个金属层互连; 第二层，包括第二单结晶晶体管并且覆盖所述至少一个金属层，其中所述至少一个金属层在所述第一半导体层和所述第二层之间; 所述第二单结晶晶体管和散热装置之间的多个热路径，其中所述多个热路径中的至少一个包括适于传导热量而不导电的热接触; 以及在所述第二层和所述至少一个金属层之间的散热层。

公开(公告)号：US09099424B1

公开(公告)日：2015-08-04

申请号：US13869115

申请日：2013-04-24

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L29/72 ,  H01L23/373

CPC classification number: H01L23/5225 ,  H01L23/3677 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A mobile system, including: a 3D device, the 3D device including: a first layer of first transistors, overlaid by at least one interconnection layer, where the interconnection layer comprises copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, the second layer including: a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to the top or bottom surface of the 3D device.

Abstract translation: 一种移动系统，包括：3D设备，所述3D设备包括：由至少一个互连层覆盖的第一层第一晶体管，所述互连层包括铜或铝; 包括第二晶体管的第二层，覆盖所述互连层的所述第二层，所述第二层包括：将所述第二晶体管与所述互连层连接的多个电连接; 以及至少一个导热和非导电接触，所述至少一个导热和非导电接触将所述第二层热连接到所述3D器件的顶表面或底表面。

公开(公告)号：US20150171079A1

公开(公告)日：2015-06-18

申请号：US14628231

申请日：2015-02-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L27/06 ,  H01L23/50 ,  H01L23/34 ,  H01L23/48

CPC classification number: H01L27/0688 ,  H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5252 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H03K19/096 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure and a second clock origin, where the second clock origin is connected to the first clock distribution structure with a plurality of through layer vias, and where the second layer thickness is less than 1 micrometer.

Abstract translation: 一种3D设备，包括：第一层，包括第一晶体管，所述第一晶体管通过第一互连层相互连接; 包括第二晶体管的第二层，覆盖第一层互连层的第二晶体管，其中第一层包括第一时钟分布结构，其中第二层包括第二时钟分布结构和第二时钟源，其中第二时钟源为 连接到具有多个通过层通孔的第一时钟分配结构，并且其中第二层厚度小于1微米。

公开(公告)号：US09029173B2

公开(公告)日：2015-05-12

申请号：US13276312

申请日：2011-10-18

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Ze'ev Wurman

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Ze'ev Wurman

IPC: H01L21/48 ,  H01L23/48 ,  H01L21/84 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L29/786 ,  H01L27/11 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  H01L23/544 ,  H01L21/683 ,  H01L21/66 ,  H01L45/00 ,  H01L27/24 ,  H01L21/762

CPC classification number: H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L21/845 ,  H01L22/22 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11803 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/249 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1683 ,  H01L2221/6835 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for formation of a semiconductor device, the method including: providing a first mono-crystalline layer including first transistors and first alignment marks; providing an interconnection layer including aluminum or copper on top of the first mono-crystalline layer; and then forming a second mono-crystalline layer on top of the first mono-crystalline layer interconnection layer by using a layer transfer step, and then processing second transistors on the second mono-crystalline layer including a step of forming a gate dielectric, where at least one of the second transistors is a p-type transistor and at least one of the second transistors is an n-type transistor.

Abstract translation: 一种形成半导体器件的方法，所述方法包括：提供包括第一晶体管和第一对准标记的第一单晶层; 在所述第一单晶层的顶部上提供包括铝或铜的互连层; 然后通过使用层转移步骤在第一单晶层互连层的顶部上形成第二单晶层，然后在第二单晶层上处理包括形成栅极电介质的步骤的第二晶体管，其中在 第二晶体管中的至少一个是p型晶体管，并且第二晶体管中的至少一个是n型晶体管。

公开(公告)号：US09023688B1

公开(公告)日：2015-05-05

申请号：US14298917

申请日：2014-06-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Albert Karl Henning

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L27/0688 ,  H01L21/67109 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for processing a semiconductor device, the method including; providing a first semiconductor layer including first transistors; forming interconnection layers overlying the transistors, where the interconnection layers include copper or aluminum; forming a shielding heat conducting layer overlaying the interconnection layers; forming an isolation layer overlaying the shielding heat conducting layer; forming a second semiconductor layer overlying the isolation layer, and processing the second semiconductor layer at a temperature greater than about 400° C., where the interconnection layers are kept at a temperature below about 400° C.

Abstract translation: 一种半导体器件的处理方法，该方法包括： 提供包括第一晶体管的第一半导体层; 形成覆盖晶体管的互连层，其中互连层包括铜或铝; 形成覆盖所述互连层的屏蔽导热层; 形成覆盖所述屏蔽导热层的隔离层; 形成覆盖隔离层的第二半导体层，以及在大于约400℃的温度下处理第二半导体层，其中互连层保持在低于约400℃的温度。

公开(公告)号：US08987079B2

公开(公告)日：2015-03-24

申请号：US13683344

申请日：2012-11-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L21/8234 ,  H01L21/4763 ,  H01L21/822 ,  H01L21/683 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/525 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L23/367 ,  H01L23/48

CPC classification number: H01L21/8221 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00015 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method for developing a custom device, the method including: programming a programmable device, where the programmable device includes a layer of monocrystalline first transistors and alignment marks, the first layer of monocrystalline first transistors is overlaid by interconnection layers, the interconnection layers are overlaid by a second layer of monocrystalline second transistors, where the interconnection layers include copper or aluminum, where the programming includes use of the second transistors, where the programming includes use of N type transistors and P type transistors, and where the programmable device includes at least one programmable connection; and then a step of producing a volume device according to a specific programmed design of the programmable device, where the volume device includes the at least one programmable connection replaced with a lithography defined connection, and where the volume device does not have the second layer.

Abstract translation: 一种用于开发定制设备的方法，所述方法包括：编程可编程设备，其中所述可编程设备包括单晶第一晶体管层和对准标记，所述第一层单晶第一晶体管由互连层覆盖，所述互连层被覆盖 通过第二层单晶第二晶体管，其中互连层包括铜或铝，其中编程包括使用第二晶体管，其中编程包括使用N型晶体管和P型晶体管，并且其中可编程器件至少包括 一个可编程连接; 然后根据可编程设备的特定编程设计产生音量设备的步骤，其中音量设备包括用光刻定义的连接替换的至少一个可编程连接，以及音量设备不具有第二层。