公开(公告)号：US09818463B2

公开(公告)日：2017-11-14

申请号：US15390681

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G06F12/00 ,  G11C8/18 ,  G11C7/10 ,  G06F13/16 ,  G06F13/42

CPC classification number: G11C8/18 ,  G06F13/161 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US20170324591A1

公开(公告)日：2017-11-09

申请号：US15490725

申请日：2017-04-18

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

IPC: H04L25/03 ,  H04B1/10 ,  H04L7/033 ,  H04L7/00

CPC classification number: H04L25/03019 ,  H04B1/1081 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

公开(公告)号：US20170315953A1

公开(公告)日：2017-11-02

申请号：US15626038

申请日：2017-06-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F13/42

Abstract: An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.

公开(公告)号：US09798628B2

公开(公告)日：2017-10-24

申请号：US14568848

申请日：2014-12-12

Applicant: Rambus Inc.

Inventor： Steven Woo ,  David Secker ,  Ravindranath Kollipara

IPC: G06F11/14 ,  G06F1/12 ,  G06F11/20 ,  G06F11/16 ,  G06F13/42

CPC classification number: G06F11/1456 ,  G06F1/12 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2058 ,  G06F13/4234 ,  G06F2201/84

Abstract: Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.

公开(公告)号：US09785500B1

公开(公告)日：2017-10-10

申请号：US15390672

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brian S. Leibowitz

IPC: G06F11/00 ,  H03M13/00 ,  G06F11/10 ,  H03M13/35

CPC classification number: G06F11/1048 ,  G06F11/1044 ,  G06F11/1076 ,  H03M13/356 ,  H03M13/6502

Abstract: A memory controller is operable in an error detection/correction mode in which N syndrome values apply to N data words of a data volume, respectively, but a single parity bit is shared across all N data words of the data volume.

公开(公告)号：US09768986B2

公开(公告)日：2017-09-19

申请号：US15209375

申请日：2016-07-13

Applicant: Rambus Inc.

Inventor： Chintan S. Thakkar ,  Kun-Yung Chang ,  Ting Wu

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03057 ,  H04L7/0045 ,  H04L7/0058 ,  H04L7/0087 ,  H04L25/03063 ,  H04L2025/03369

Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

公开(公告)号：US09768947B2

公开(公告)日：2017-09-19

申请号：US15339342

申请日：2016-10-31

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Brian Leibowitz ,  Jihong Ren

IPC: H04L7/00 ,  H04L27/32 ,  H04L27/00

CPC classification number: H04L7/0016 ,  H03L7/1974 ,  H03L7/235 ,  H04L7/033 ,  H04L27/0014 ,  H04L27/32 ,  H04L2027/0016 ,  H04L2027/0036 ,  H04L2027/0053 ,  H04L2027/0055 ,  H04L2027/0067

Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

公开(公告)号：US09767918B2

公开(公告)日：2017-09-19

申请号：US15282932

申请日：2016-09-30

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/00 ,  G11C29/12 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/00 ,  G06F3/06 ,  G06F12/0897 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G11C2029/3202 ,  Y02D10/13 ,  Y02D10/14

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A defect circuit may generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.

公开(公告)号：US20170256290A1

公开(公告)日：2017-09-07

申请号：US15603333

申请日：2017-05-23

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/06 ,  H01L23/48 ,  H01L27/108 ,  H01L25/065 ,  G11C5/02

CPC classification number: G11C5/063 ,  G11C5/025 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/10897 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US09735898B2

公开(公告)日：2017-08-15

申请号：US14861573

申请日：2015-09-22

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

IPC: G06F19/00 ,  H04B17/11 ,  H04L5/14 ,  H04L25/03

CPC classification number: H04B17/11 ,  H04L5/1438 ,  H04L25/03343 ,  H04L2025/03802

Abstract: A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.