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    Reference voltage generation and calibration for single-ended signaling
    401.
    发明授权
    Reference voltage generation and calibration for single-ended signaling 有权
    单端信号的参考电压产生和校准

    公开(公告)号：US09166838B1

    公开(公告)日：2015-10-20

    申请号：US14489814

    申请日：2014-09-18

    Applicant: Rambus Inc.

    Inventor： Lei Luo ,  Barry W. Daly ,  Kambiz Kaviani ,  John Cronan Eble, III ,  John Wilson

    IPC: H03K9/00 ,  H04L27/06 ,  H04L25/06 ,  H03K3/013 ,  H04L25/08

    CPC classification number: H03K3/013 ,  G11C5/147 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  H04L25/0296 ,  H04L25/06 ,  H04L25/08

    Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

    Abstract translation: 发射机上的信号以与电源的正节点分离的方式跟踪接地节点上的噪声。 信号从发射机发射到接收机。 在接收机上产生参考电压以跟踪接收机中接地节点上的噪声。 因此，接收信号和参考电压具有基本上相同的噪声特性，这些噪声特性成为当这两个信号彼此进行比较时可以消除的共模噪声。 在另一实施例中，将参考电压与预定校准图案进行比较。 基于采样器输出和预定校准图案之间的差异产生误差信号。 然后使用误差信号来调整参考电压，使得参考电压的直流电平基本上位于接收信号的中间。

    Memory system components that support error detection and correction
    404.
    发明授权
    Memory system components that support error detection and correction 有权
    支持错误检测和校正的内存系统组件

    公开(公告)号：US09165621B2

    公开(公告)日：2015-10-20

    申请号：US14160290

    申请日：2014-01-21

    Applicant: Rambus Inc.

    Inventor： Richard E. Perego

    IPC: G11C8/00 ,  G06F11/10 ,  G11C29/04

    CPC classification number: G11C8/00 ,  G06F11/1016 ,  G06F11/1048 ,  G11C2029/0411

    Abstract: The disclosed embodiments relate to components of a memory system that support error detection and correction by means of storage and retrieval of error correcting codes. In specific embodiments, this memory system includes a memory device, which further contains a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. Moreover, the memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first row address and the second row address to a first row decoder and a second row decoder in the memory bank, respectively. Finally, the memory device uses the first row decoder to decode the first row address to access the first row and concurrently uses the second row decoder to decode the second row address to access the second row.

    Abstract translation: 所公开的实施例涉及通过存储和检索纠错码支持错误检测和校正的存储器系统的组件。 在具体实施例中，该存储器系统包括还包含存储体的存储器件。 在操作期间，存储器装置接收同时访问存储器组的第一存储区域中的第一行的数据字的请求以及与存储器组的第二存储区域中的第二行与数据相关联的错误信息。 此外，存储器请求包括标识第一行的第一行地址和标识第二行的第二行地址。 接下来，存储器件分别将第一行地址和第二行地址路由到存储体中的第一行解码器和第二行解码器。 最后，存储装置使用第一行解码器对第一行地址进行解码以访问第一行，同时使用第二行解码器解码第二行地址以访问第二行。

    Integrated circuit comprising a delay-locked loop
    405.
    发明授权
    Integrated circuit comprising a delay-locked loop 有权
    集成电路包括延迟锁定环路

    公开(公告)号：US09160350B2

    公开(公告)日：2015-10-13

    申请号：US13676945

    申请日：2012-11-14

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Masum Hossain ,  Pak S. Chau

    IPC: H03L7/06 ,  H03L7/091 ,  G11C8/18 ,  H03K5/156 ,  H03L7/08 ,  H03L7/081 ,  H03L7/083 ,  H03L7/099 ,  H03L7/10 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04

    CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/222 ,  G11C8/18 ,  H03K5/1565 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/083 ,  H03L7/0995 ,  H03L7/104

    Abstract: Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.

    Abstract translation: 描述了包括延迟锁定环（DLL）的集成电路（IC）的实施例。 一些实施例包括通过将输入时钟信号延迟第一延迟来产生第一时钟信号的第一电路，基于输入时钟信号和第一时钟信号确定代码的第二电路，以及基于输出时钟信号的第三电路 对输入时钟信号和代码。 在一些实施例中，通过在大多数时间内断电DLL电路的至少一些部分来降低DLL电路的功耗。 在一些实施例中，用于对存储器件的命令和地址电路进行时钟的时钟信号用于对片上终端等待时间计数器电路进行时钟。

    Dynamic deterministic address translation for shuffled memory spaces
    406.
    发明授权
    Dynamic deterministic address translation for shuffled memory spaces 有权
    混洗存储空间的动态确定性地址转换

    公开(公告)号：US09158672B1

    公开(公告)日：2015-10-13

    申请号：US13644550

    申请日：2012-10-04

    Applicant: Rambus Inc.

    Inventor： Hongzhong Zheng ,  Brent Steven Haukness

    IPC: G06F12/00 ,  G06F12/02

    CPC classification number: G06F12/0246 ,  G06F12/023 ,  G06F12/0238 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7211

    Abstract: A memory storage scheme specially adapted for wear leveling (or other reorganization of logical memory space). Memory space includes a logical memory space of M addressable blocks of data, stored as rows or pages, and N substitute rows or pages. Data is periodically shuffled by copying data from one of the M addressable blocks to a substitute row, with the donating row then becoming part of substitute memory space, available for ensuing wear leveling operations, using a stride address. The disclosed techniques enable equation-based address translation, obviating need for an address translation table. An embodiment performs address translation entirely in hardware, for example, integrated with a memory device to perform wear leveling or data scrambling, in a manner entirely transparent to a memory controller. In addition, the stride address can represent an offset greater than one (e.g., greater than one row) and can be dynamically varied.

    Abstract translation: 专门用于磨损均衡（或逻辑内存空间的其他重组）的存储器存储方案。 存储器空间包括存储为行或页面的M个可寻址数据块的逻辑存储空间，以及N个替代行或页面。 通过将数据从M个可寻址块中的一个复制到替代行来周期性地进行数据洗牌，然后捐赠行成为替代存储器空间的一部分，可用于随后进行的磨损均衡操作，使用跨步地址。 所公开的技术使得基于方程式的地址转换不需要地址转换表。 一个实施例，以对于存储器控制器完全透明的方式，完全在硬件上执行地址转换，例如与存储器件集成以执行损耗均衡或数据加扰。 此外，步幅地址可以表示大于1的偏移（例如，大于一行），并且可以动态地变化。

    Equalizing transmitter and method of operation
    408.
    发明授权
    Equalizing transmitter and method of operation 有权
    发射机均衡和操作方法

    公开(公告)号：US09148313B2

    公开(公告)日：2015-09-29

    申请号：US12522308

    申请日：2008-01-07

    Applicant: John Wood Poulton

    Inventor： John Wood Poulton

    IPC: H04L27/28 ,  H04L25/02 ,  H04L25/03

    CPC classification number: H04L25/03878 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0288 ,  H04L25/03343 ,  H04L2025/03808

    Abstract: A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.

    Abstract translation: 一种用于提供信道均衡的发射机，其包括具有高通滤波器的第一驱动器和第二驱动器。 第一驱动器产生表示数字输入信号的第一输出信号。 第二驱动器产生表示数字输入信号的高通滤波版本的第二输出信号。 将第一和第二输出信号相加以提供信道均衡以用于在信道上传输的第三输出信号。

    Sharing a check bit memory device between groups of memory devices
    409.
    发明授权
    Sharing a check bit memory device between groups of memory devices 有权
    在存储器设备组之间共享一个校验位存储器件

    公开(公告)号：US09141472B2

    公开(公告)日：2015-09-22

    申请号：US13610675

    申请日：2012-09-11

    Applicant: Thomas J. Giovannini ,  Ian Shaeffer

    Inventor： Thomas J. Giovannini ,  Ian Shaeffer

    IPC: G11C29/00 ,  G06F11/10 ,  H03M13/09

    CPC classification number: G06F11/1044 ,  H03M13/09

    Abstract: A memory system that supports error detection and correction (EDC) coverage. The memory system includes a memory module with at least two groups of memory devices that store data and another memory device that stores error checking information (e.g., Error Correcting Code) for both groups of memory devices. The memory module also includes a memory buffer that determines an address for accessing the error checking information based on whether data is transferred with the first group of memory devices or the second group of memory devices. Alternatively, the memory controller may determine the address for accessing the error checking information to reduce or eliminate the need for a memory buffer.

    Abstract translation: 支持错误检测和纠正（EDC）覆盖的内存系统。 存储器系统包括具有存储数据的至少两组存储器件的存储器模块和用于存储两组存储器件的错误校验信息（例如，纠错码）的另一个存储器件。 存储器模块还包括存储器缓冲器，其基于是否利用第一组存储器件或第二组存储器件传送数据来确定用于访问错误检查信息的地址。 或者，存储器控制器可以确定用于访问错误检查信息的地址以减少或消除对存储器缓冲器的需要。

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