公开(公告)号：US20160093662A1

公开(公告)日：2016-03-31

申请号：US14953973

申请日：2015-11-30

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Laurent Frey

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L31/02327 ,  H01L31/035236 ,  H01L31/107

Abstract: A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape.

公开(公告)号：US20160056612A1

公开(公告)日：2016-02-25

申请号：US14827429

申请日：2015-08-17

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thomas Ferrotti ,  Badhise Ben Bakir ,  Alain Chantre ,  Sebastien Cremer ,  Helene Duprez

IPC: H01S5/12 ,  H01S5/02 ,  H01S5/343

CPC classification number: H01S5/1237 ,  G02B6/30 ,  G02B6/34 ,  G02B2006/12061 ,  G02B2006/12121 ,  H01L2224/32 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/02284 ,  H01S5/026 ,  H01S5/0421 ,  H01S5/1014 ,  H01S5/1032 ,  H01S5/1231 ,  H01S5/187 ,  H01S5/323 ,  H01S5/343 ,  H01S2301/166

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising:a III-V heterostructure gain medium (3); andan optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon.The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

Abstract translation: 本发明涉及一种布置在硅中和/或硅上的III-V异质结构激光器件，包括：III-V异质结构增益介质; 以及面向所述增益介质（3）布置并包括配备有纵向肋（17）的平板波导（15）的光学肋波导（11），所述光学波纹管（11）布置在所述硅中。 光学肋波导（11）被定向成使得至少一个布拉格光栅（19,19a，19b）布置在相对于增益介质（3）近端的平板波导（15）的该侧（21）上， 因为肋（17）被放置在相对于增益介质（3）远端的平板波导（15）的该侧（23）上。

公开(公告)号：US09268743B2

公开(公告)日：2016-02-23

申请号：US13949884

申请日：2013-07-24

Applicant: STMicroelectronics SA

Inventor： Jean-Robert Manouvrier

IPC: G06F17/50 ,  G06F17/10

CPC classification number: G06F17/10 ,  G06F17/5036

Abstract: The electric behavior of a reverse-biased PN junction diode is modeled by measuring the value of voltage V present across the diode and the value of the corresponding current I running through this diode, the voltage V varying within a range of values including the value of diode breakdown voltage. A representation of a function ln ⁡ ( I - I s ) according to voltage V is established from the measured values of current I and of voltage V, IS being the saturation current of the diode. A linear function representative of a substantially linear portion of the function, characterized by voltages V greater than breakdown voltage VBK in terms of absolute value, is determined. An avalanche multiplication factor MM is then calculated by MM = 1 + ⅇ ( - slbv · V + bv bv ) , with parameter slbv equal to the ordinate at the origin of the linear function, and parameter slbv/bv equal to the slope of the linear function.

Abstract translation: 反向偏置PN结二极管的电气行为通过测量二极管上存在的电压V的值和通过该二极管的相应电流I的值来建模，电压V在包括的值的范围内变化 二极管击穿电压。 根据电压I和电压V的测量值建立函数ln⁡（I-I s）的表示，IS是二极管的饱和电流。 确定表示功能的基本线性部分的线性函数，其特征在于以绝对值计的大于击穿电压VBK的电压V。 然后通过MM = 1 +ⅇ（ - slbv·V + bv bv）计算雪崩倍增因子MM，参数slbv等于线性函数原点的纵坐标，参数slbv / bv等于 线性函数。

公开(公告)号：US20160047692A1

公开(公告)日：2016-02-18

申请号：US14925753

申请日：2015-10-28

Applicant: STMicroelectronics SA

Inventor： Hani Sherry ,  Andreia Cathelin ,  Andreas Kaiser ,  Ullrich Pfeiffer ,  Janusz Grzyb ,  Yan Zhao

IPC: G01J5/22

CPC classification number: G01J5/22 ,  G01J5/10 ,  G01J5/20 ,  G01J2005/0077 ,  G01J2005/202 ,  G01N21/3581 ,  H01Q23/00 ,  Y10T29/49018

Abstract: A terahertz imager includes an array of pixel circuits. Each pixel circuit has an antenna and a detector. The detector is coupled to differential output terminals of the antenna. A frequency oscillator is configured to generate a frequency signal on an output line. The output line is coupled to an input terminal of the antenna of at least one of the pixel circuits.

Abstract translation: 太赫兹成像器包括像素电路阵列。 每个像素电路具有天线和检测器。 检测器耦合到天线的差分输出端。 频率振荡器被配置为在输出线上产生频率信号。 输出线耦合到至少一个像素电路的天线的输入端。

公开(公告)号：US09264076B2

公开(公告)日：2016-02-16

申请号：US14177371

申请日：2014-02-11

Applicant: STMICROELECTRONICS SA ,  INSTITUT POLYTECHNIQUE DE BORDEAUX ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  UNIVERSITE DE BORDEAUX

Inventor： Didier Belot ,  Yann Deval ,  Francois Rivet

IPC: G06F1/04 ,  H03K3/00 ,  H04B1/00 ,  H04B1/403 ,  H04B1/04

CPC classification number: H04B1/0014 ,  H04B1/406 ,  H04B2001/0491

Abstract: A device for generating a signal, including: a balun; and a circuit capable of summing up, on a first access terminal of the balun, currents representative of signals received on first input terminals of the device, and on a second access terminal of the balun, currents representative of signals received on second input terminals of the device.

Abstract translation: 一种用于产生信号的装置，包括：平衡 - 不平衡转换器; 以及能够在所述平衡 - 不平衡变换器的第一接入终端上总和的电流，代表在所述设备的第一输入端子上接收的信号的电流，以及在所述平衡 - 不平衡变换器的第二接入终端上的总和的电流， 装置。

公开(公告)号：US09257526B2

公开(公告)日：2016-02-09

申请号：US14313836

申请日：2014-06-24

Applicant: STMicroelectronics SA

Inventor： Pierre Boulenc

IPC: H01L29/66 ,  H01L21/8249 ,  H01L29/732 ,  H01L29/06 ,  H01L29/739 ,  H01L29/08

CPC classification number: H01L29/66333 ,  H01L21/8249 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/7325 ,  H01L29/7395

Abstract: The present disclosure relates to a method for manufacturing a bipolar transistor. The method forms a trench to isolate a first region from a second region in a semiconductor wafer, and to isolate these regions from the rest of the wafer. The method forms first P-doped well in the second region and produces a collector region of second and third wells by a P doping in the first region. The second well is in contact with the first well below the trench. The method also produces an N-doped base well on the collector region and, at the wafer surface, and forms a CMOS transistor gate on the first region and delimiting a third region and a fourth region. The method also forms a P+-doped collector contact region in the first well, forms a P+ doped emitter region in the third region, and forms an N+-doped base contact region in the fourth region.

Abstract translation: 本公开涉及一种用于制造双极晶体管的方法。 该方法形成沟槽以将第一区域与半导体晶片中的第二区域隔离，并将这些区域与晶片的其余部分隔离。 该方法在第二区域中形成第一P掺杂阱，并且在第一区域中通过P掺杂产生第二阱和第三阱的集电极区。 第二个井与沟槽下面的第一个井接触。 该方法还在集电极区域和晶片表面上产生N掺杂的基极阱，并在第一区域上形成CMOS晶体管栅极并限定第三区域和第四区域。 该方法还在第一阱中形成P +掺杂的集电极接触区，在第三区中形成P +掺杂的发射极区，并在第四区中形成N +掺杂的基极接触区。

公开(公告)号：US20160033260A1

公开(公告)日：2016-02-04

申请号：US14661907

申请日：2015-03-18

Applicant: STMicroelectronics SA

Inventor： Stéphane Valente

IPC: G01B11/14 ,  G06N7/00 ,  G06F3/042 ,  G01S17/08

CPC classification number: G01B11/14 ,  G01S17/08 ,  G06F3/017 ,  G06F3/0304 ,  G06F3/042 ,  G06N7/005

Abstract: The method for processing signals originating for example from several proximity sensors for the recognition of a movement of an object, comprises first respective samplings of the said signals delivered by the sensors so as to obtain a first set of first date-stamped samples, the generation, from the first set of first date-stamped samples, of new sampling times comprising a start of movement time, an end of movement time, and times regularly spaced between the start of movement time and the end of movement time, a re-sampling of the signal delivered by each sensor between the start of movement time and the end of movement time at the said new sampling times using the first samples, in such a manner as to generate a second set of second date-stamped samples, and a processing of the said second set of date-stamped samples by a movement recognition algorithm.

Abstract translation: 用于处理例如来自几个接近传感器的信号的方法，用于识别物体的移动，包括由传感器传送的所述信号的第一个相应采样，以便获得第一组初始加盖日期的采样， 从第一组初始日期标记的样本中，包括移动时间的开始，移动时间结束以及移动时间开始与移动时间结束之间规则间隔的时间的新采样时间，重新采样 在使用第一采样的所述新采样时间之间，在移动时间开始和移动时间结束之间由每个传感器传送的信号以产生第二组第二日期戳样本的方式，以及处理 的所述第二组日期戳样本通过运动识别算法。

公开(公告)号：US09240466B2

公开(公告)日：2016-01-19

申请号：US14451174

申请日：2014-08-04

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Denis Rideau ,  Olivier Nier

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L29/66772 ,  H01L21/0217 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/785

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract translation: 本公开涉及一种对半导体层施加应力的方法，包括：在绝缘体上的结构上形成绝缘体结构，该绝缘体上硅结构具有与绝缘层相接触的半导体层，一个或多个与晶体管沟道所在半导体层的第一区对准的应力块 形成，其中所述应力块被应力，使得它们局部应力所述半导体层; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。

公开(公告)号：US09231642B2

公开(公告)日：2016-01-05

申请号：US14191037

申请日：2014-02-26

Applicant: STMicroelectronics SA

Inventor： Baudouin Martineau ,  Olivier Richard ,  Frederic Gianesello

IPC: H04B1/44 ,  H04B1/40 ,  H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/24 ,  H03F3/60 ,  H03F3/68 ,  H03F3/189 ,  H03F3/20

CPC classification number: H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/189 ,  H03F3/19 ,  H03F3/20 ,  H03F3/211 ,  H03F3/24 ,  H03F3/602 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/21106 ,  H04B1/40

Abstract: A multichannel splitter formed from 1 to 2 splitters. An input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter. The 1 to 2 splitters are electrically series-connected. First respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter.

Abstract translation: 一个由1到2个分路器组成的多通道分路器。 第一个1到2个分配器的输入端定义了多通道分离器的输入。 1至2个分离器电气串联连接。 1到2个分路器的第一个相应的输出定义了多通道分路器的输出端子。

公开(公告)号：US09224708B2

公开(公告)日：2015-12-29

申请号：US14339630

申请日：2014-07-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Jean-Philippe Colonna ,  Perceval Coudrain

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/306 ,  H01L21/48 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L24/19 ,  H01L21/30604 ,  H01L21/4853 ,  H01L21/6836 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13186 ,  H01L2224/1356 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2224/14181 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract translation: 本发明涉及一种用于在导电元件上制造互连焊盘的方法，包括上表面和侧壁; 所述方法从至少其上表面绝缘的衬底执行; 所述导电元件至少穿过所述基板的绝缘部分，所述方法的特征在于，其包括以下步骤的顺序：对所述导电元件进行压花的步骤，在所述基板的上绝缘面上方形成步骤 ，包括至少一个导电层和一个电阻层的层叠层，部分去除所述电阻层的步骤，在所述导电层的所述部分上的电解生长步骤，以便形成至少一个互连衬垫 在所述导电元件上。