公开(公告)号：US20180053553A1

公开(公告)日：2018-02-22

申请号：US15238681

申请日：2016-08-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2216/04 ,  G11C2216/22

Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.

公开(公告)号：US09887206B2

公开(公告)日：2018-02-06

申请号：US15453829

申请日：2017-03-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L21/336 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

公开(公告)号：US20180005701A1

公开(公告)日：2018-01-04

申请号：US15706586

申请日：2017-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Xiao Yan Pi ,  Xiaozhou Qian ,  Kai Man Yue ,  Yao Zhou ,  Yaohua Zhu

IPC: G11C16/28 ,  G11C7/12 ,  G11C29/02 ,  G11C16/08 ,  G11C7/14 ,  G11C16/24 ,  G11C7/06 ,  G11C29/50 ,  G11C29/12

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C16/08 ,  G11C16/24 ,  G11C29/025 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.

公开(公告)号：US09767923B2

公开(公告)日：2017-09-19

申请号：US15272417

申请日：2016-09-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten

IPC: G11C16/06 ,  G11C29/00 ,  G11C5/02 ,  G11C5/06 ,  G11C16/30 ,  G11C29/26 ,  G11C16/04 ,  G11C16/26 ,  G11C7/04 ,  G11C29/02 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C29/76 ,  G11C5/02 ,  G11C5/06 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/26 ,  G11C2213/71 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A three-dimensional flash memory system is disclosed.

公开(公告)号：US09721958B2

公开(公告)日：2017-08-01

申请号：US15003659

申请日：2016-01-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Chun-Ming Chen ,  Man-Tang Wu ,  Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L21/336 ,  H01L27/11524 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11536 ,  H01L21/306

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

公开(公告)号：US20170125603A1

公开(公告)日：2017-05-04

申请号：US15294174

申请日：2016-10-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Jeng-Wei Yang ,  Nhan Do

IPC: H01L29/788 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7883 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66825

Abstract: A non-volatile memory cell that includes a silicon substrate, source and drain regions formed in the silicon substrate (where a channel region of the substrate is defined between the source and drain regions), a metal floating gate disposed over and insulated from a first portion of the channel region, a metal control gate disposed over and insulated from the metal floating gate, a polysilicon erase gate disposed over and insulated from the source region, and a polysilicon word line gate disposed over and insulated from a second portion of the channel region.

公开(公告)号：US09640263B2

公开(公告)日：2017-05-02

申请号：US14140452

申请日：2013-12-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Sakhawat M. Khan

IPC: G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C27/00 ,  G11C13/00

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C27/005 ,  G11C2211/5634

Abstract: A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

公开(公告)号：US20170117285A1

公开(公告)日：2017-04-27

申请号：US15290960

申请日：2016-10-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Chun-Ming Chen ,  Man-Tang Wu ,  Jeng-Wei Yang ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788

Abstract: A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

公开(公告)号：US20170103991A1

公开(公告)日：2017-04-13

申请号：US15264457

申请日：2016-09-13

Applicant: Silicon Storage Technology, Inc.

Inventor： JINHO KIM ,  CHIEN-SHENG SU ,  FENG ZHOU ,  XIAN LIU ,  NHAN DO ,  PRATEEP TUNTASOOD ,  PARVIZ GHAZAVI

IPC: H01L27/115

CPC classification number: H01L27/11531 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

Abstract: A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.

公开(公告)号：US09620235B2

公开(公告)日：2017-04-11

申请号：US14772047

申请日：2013-03-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Yao Zhou ,  Kai Man Yue ,  Xiaozhou Qian ,  Bin Sheng

IPC: G11C16/06 ,  G11C16/28 ,  G11C7/08 ,  G11C8/18 ,  G11C16/26 ,  G11C16/24 ,  G11C16/32 ,  G11C7/22

CPC classification number: G11C16/28 ,  G11C7/08 ,  G11C7/227 ,  G11C8/18 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: A self-timer for a sense amplifier in a memory device is disclosed.