公开(公告)号：US07498236B2

公开(公告)日：2009-03-03

申请号：US11563715

申请日：2006-11-28

Applicant: Steven R. Codding ,  Timothy C. Krywanczyk ,  Edmund J. Sprogis

Inventor： Steven R. Codding ,  Timothy C. Krywanczyk ,  Edmund J. Sprogis

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/306 ,  C23F1/00

CPC classification number: H01L21/78

Abstract: Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of the silicon wafer. The building step includes the steps of forming a desired structure in the wafer, and forming an end structure in the wafer, said end structure extending to a greater depth, toward the back side of the wafer, than the desired structure. Also, the removing step includes the step of removing said substrate only to the end structure, whereby no part of the desired structure is removed during the removing step.

Abstract translation: 公开了用于制造半导体晶片的方法和系统。 该方法包括以下步骤：提供具有正面和背面的硅晶片，在晶片前侧构建集成电路，然后从硅晶片的背面去除衬底。 构建步骤包括以下步骤：在晶片中形成期望的结构，并且在晶片中形成端部结构，所述端部结构延伸到比晶片的背面更大的深度，而不是期望的结构。 此外，除去步骤包括仅将该基材除去至端部结构的步骤，由此在除去步骤期间不除去所需结构的一部分。

公开(公告)号：US20090045502A1

公开(公告)日：2009-02-19

申请号：US11838917

申请日：2007-08-15

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Edmund J. Sprogis

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L23/3157 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.

Abstract translation: 形成有可以与衬底隔离或电连接的通孔形成的半导体芯片级封装，以及可以隔离或电连接到衬底的具有通孔的半导体芯片级封装的制造方法。

公开(公告)号：US20080303139A1

公开(公告)日：2008-12-11

申请号：US11759651

申请日：2007-06-07

Applicant: Kerry Bernstein ,  Timothy J. Dalton ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Richard Q. Williams

Inventor： Kerry Bernstein ,  Timothy J. Dalton ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Richard Q. Williams

IPC: H01L23/34 ,  H01L21/00

CPC classification number: H01L23/585 ,  H01L23/13 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13025 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/484 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2224/78 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.

Abstract translation: 一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。 此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

公开(公告)号：US20080124835A1

公开(公告)日：2008-05-29

申请号：US11534366

申请日：2006-11-03

Applicant: Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

Inventor： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC: H01L21/50

CPC classification number: H01L25/50 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

公开(公告)号：US20080088014A1

公开(公告)日：2008-04-17

申请号：US11528227

申请日：2006-09-26

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US07067914B2

公开(公告)日：2006-06-27

申请号：US09683027

申请日：2001-11-09

Applicant: John C. Malinowski ,  Edmund J. Sprogis ,  Steven H. Voldman

Inventor： John C. Malinowski ,  Edmund J. Sprogis ,  Steven H. Voldman

IPC: H01L23/34

CPC classification number: H01L23/60 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed is an electronic device comprising a semiconductor chip including an integrated circuit having at least one electrostatic discharge sensitive device and a non-semiconductor chip, positioned in close proximity to the semiconductor chip, the non-semiconductor chip having at least one electrostatic discharge protection device. The electrostatic discharge protection device is electrically connected to the electrostatic discharge sensitive device.

公开(公告)号：US20130307656A1

公开(公告)日：2013-11-21

申请号：US13474239

申请日：2012-05-17

Applicant: Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Michael J. Shapiro ,  Edmund J. Sprogis

Inventor： Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Michael J. Shapiro ,  Edmund J. Sprogis

IPC: H01F27/40 ,  H01F7/06 ,  H01F27/28

CPC classification number: H01L23/5227 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/30107 ,  Y10T29/49071 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A distributed active transformer is provided comprising a primary and a secondary winding. The primary winding comprises a first set of conductive vias extending in a direction between a first surface and a second surface of an element, a first set of first electrically conductive lines extending along the first surface, and a first set of second electrically conductive lines extending along the second surface. The secondary winding comprises a second set of conductive vias extending in a direction between the first surface and the second surface, a second set of first electrically conductive lines extending along the first surface, and a second set of second electrically conductive lines extending along the second surface. When energized, the primary winding generates magnetic flux extending in a direction parallel to the first surface and the second surface. The secondary winding receives energy transferred by the magnetic flux generated by the primary winding.

Abstract translation: 提供一种分布式有源变压器，其包括初级和次级绕组。 初级绕组包括在元件的第一表面和第二表面之间的方向上延伸的第一组导电通孔，沿着第一表面延伸的第一组第一导电线，以及延伸的第一组第二导电线 沿着第二个表面。 次级绕组包括在第一表面和第二表面之间的方向上延伸的第二组导电通孔，沿着第一表面延伸的第二组第一导电线，以及沿着第二表面延伸的第二组第二导电线 表面。 当通电时，初级绕组产生沿平行于第一表面和第二表面的方向延伸的磁通量。 次级绕组接收由初级绕组产生的磁通传递的能量。

公开(公告)号：US08492816B2

公开(公告)日：2013-07-23

申请号：US12685156

申请日：2010-01-11

Applicant: James S. Nakos ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： James S. Nakos ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L28/40 ,  H01L29/66181 ,  H01L29/945

Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.

Abstract translation: 公开了用于形成硅化深沟槽去耦电容器的解决方案。 一方面，半导体结构在硅衬底内包括沟槽电容器，所述沟槽电容器包括：延伸到硅衬底中的外沟槽; 介电衬垫层，与所述外沟槽接触; 所述掺杂多晶硅层在所述外部沟槽内形成内部沟槽; 以及在所述掺杂多晶硅层的一部分上的硅化物层，所述硅化物层将所述接触的至少一部分与所述掺杂多晶硅层的至少一部分分离; 以及具有与所述沟槽电容器邻接的下表面的接触件，所述下表面的一部分不邻接所述硅化物层。

公开(公告)号：US20120181700A1

公开(公告)日：2012-07-19

申请号：US13005883

申请日：2011-01-13

Applicant: Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

Inventor： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

IPC: H01L23/48 ,  G06F17/50

CPC classification number: H01L21/76898 ,  G06F17/5068 ,  G06F2217/80 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

Abstract translation: 本发明的实施例提供了具有减少的通过硅通孔（TSV）的应力和相关IC设计结构和方法的集成电路（IC）。 在一个实施例中，本发明包括设计具有降低的衬底应力的集成电路（IC）的方法，所述方法包括：在IC设计文件中放置多个通过硅通孔（TSV）占位符单元，每个占位符单元具有未定义的 TSV方向 用具有第一取向的第一组TSV单元替换所述多个TSV占位符单元的第一部分; 以及用具有基本上垂直于第一取向的第二取向的第二组TSV单元替换多个TSV占位符单元的第二部分，其中具有第一取向的TSV单元和具有第二取向的TSV单元分散以减少TSV 在IC衬底中引起的应力。

公开(公告)号：US08097492B2

公开(公告)日：2012-01-17

申请号：US12344095

申请日：2008-12-24

Applicant: John H. Magerlein ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Herbert I. Stoller

Inventor： John H. Magerlein ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Herbert I. Stoller

IPC: H01L21/50

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/147 ,  H01L24/16 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

Abstract translation: 基于硅的封装（SBP）由从作为SBP的基底的厚晶片开始形成，该基板由具有平坦的第一表面和反面的硅组成。 然后形成包括与第一表面接触的金属捕获结构和在第一表面上的多层导体图案的互连结构。 在SBP和晶片保持器之间形成临时结合，晶片保持器是刚性结构。 将晶圆的反面变薄到所需的厚度，以形成用于SBP的超薄硅晶片（UTSW）。 通过具有锥形或垂直侧壁的孔形成，其延伸穿过UTSW以到达金属捕获结构。 然后在穿过UTSW的通孔中形成金属焊盘，使其与金属捕获结构电接触。 然后将通孔中的金属焊盘接合到载体的焊盘。