公开(公告)号：US07067914B2

公开(公告)日：2006-06-27

申请号：US09683027

申请日：2001-11-09

申请人： John C. Malinowski ,  Edmund J. Sprogis ,  Steven H. Voldman

发明人： John C. Malinowski ,  Edmund J. Sprogis ,  Steven H. Voldman

IPC分类号： H01L23/34

CPC分类号： H01L23/60 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is an electronic device comprising a semiconductor chip including an integrated circuit having at least one electrostatic discharge sensitive device and a non-semiconductor chip, positioned in close proximity to the semiconductor chip, the non-semiconductor chip having at least one electrostatic discharge protection device. The electrostatic discharge protection device is electrically connected to the electrostatic discharge sensitive device.

公开(公告)号：US06429045B1

公开(公告)日：2002-08-06

申请号：US09779215

申请日：2001-02-07

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  H. Bernhard Pogge ,  Edmund J. Sprogis ,  Steven H. Voldman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  H. Bernhard Pogge ,  Edmund J. Sprogis ,  Steven H. Voldman

IPC分类号： H01L2144

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L23/544 ,  H01L24/81 ,  H01L25/0655 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81136 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  Y10S438/928 ,  H01L2924/00012

摘要： A technique for fabricating precision aligned macros (PAMs) with reduced risk of electrostatic discharge damage and thermal damage. An electrical and thermal contact is provided through the back of the individual chips to a supporting silicon substrate. A conductive seed layer for electroplating is formed on a support substrate. A dielectric (preferably, a thermid) layer is formed on the seed layer. Vias are formed in the thermid layer and metal contacts are formed in the vias. The front faces of two or more chips are bonded onto the top surface of an alignment substrate, and the chips are aligned to the alignment substrate. The back faces of the chips are bonded to the metal contacts and thermid layer with heat and pressure. The alignment substrate is removed. The front faces of the chips are planarized. Finally, interconnect wiring is formed over the chips and thermid layer.

摘要翻译： 一种制造精密对准宏（PAM）的技术，降低了静电放电损伤和热损伤的风险。 通过单个芯片的背面提供电接触和热接触到支撑硅衬底。 用于电镀的导电种子层形成在支撑衬底上。 在种子层上形成电介质（优选为热）层。 通孔形成在热层中，金属触点形成在通孔中。 将两个以上的芯片的正面接合在取向基板的顶面上，将芯片与取向基板对准。 芯片的背面通过热和压力结合到金属触点和热层。 取出对准基板。 芯片的正面平面化。 最后，在芯片和热层上形成互连布线。

公开(公告)号：US09368410B2

公开(公告)日：2016-06-14

申请号：US12033280

申请日：2008-02-19

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Edmund J. Sprogis

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Edmund J. Sprogis

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/76205 ,  H01L21/823878 ,  H01L29/7846

摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.

摘要翻译： 公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。 该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。 该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。 第一氧化沟槽在通道中产生应变分量以增加器件性能。

公开(公告)号：US09105627B2

公开(公告)日：2015-08-11

申请号：US13289071

申请日：2011-11-04

申请人： Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

发明人： Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

IPC分类号： H01F5/00 ,  H01L27/08 ,  H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F17/00 ,  H01F41/00

CPC分类号： H01L23/49822 ,  H01F17/0013 ,  H01F41/005 ,  H01F2017/0086 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00

摘要： A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

摘要翻译： 提供了一种结合线圈电感器的线圈电感器和降压稳压器，其可以制造在诸如半导体芯片的微电子元件上，或者在诸如半导体，玻璃或陶瓷插入元件的互连元件上。 当通电时，线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量，并且其峰值磁通量设置在第一和第二表面之间。 在一个示例中，线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成，沿着微电子或互连元件的第二表面延伸的第二导电线，以及多个导电通孔， 通过硅通孔，在微电子或互连元件的厚度方向上延伸。 还提供了制造线圈电感器的方法。

公开(公告)号：US09040390B2

公开(公告)日：2015-05-26

申请号：US13483663

申请日：2012-05-30

申请人： Timothy H. Daubenspeck ,  Steven E. Molis ,  Gordon C. Osborne, Jr. ,  Wolfgang Sauter ,  Edmund J. Sprogis

发明人： Timothy H. Daubenspeck ,  Steven E. Molis ,  Gordon C. Osborne, Jr. ,  Wolfgang Sauter ,  Edmund J. Sprogis

IPC分类号： H01L21/46 ,  H01L21/683 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L25/065

CPC分类号： H01L21/6835 ,  H01L21/486 ,  H01L21/76829 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2225/06513 ,  H01L2225/06517 ,  Y10S438/976 ,  H01L2924/014

摘要： A releasable buried layer for 3-D fabrication and methods of manufacturing is disclosed. The method includes forming an interposer structure which includes forming a carbon rich dielectric releasable layer over a wafer. The method further includes forming back end of the line (BEOL) layers over the carbon rich dielectric layer, including wiring layers and solder bumps. The method further includes bonding the solder bumps to a substrate using flip chip processes. The flip chip processes comprises reflowing the solder bumps and rapidly cooling down the solder bumps which releases the carbon rich dielectric releasable layer from the wafer.

摘要翻译： 公开了用于3-D制造的可释放掩埋层和制造方法。 该方法包括形成中间层结构，其包括在晶片上形成富含碳的电介质可剥离层。 该方法还包括在富含碳的电介质层上形成线（BEOL）层的后端，包括布线层和焊料凸块。 该方法还包括使用倒装芯片工艺将焊料凸块接合到衬底上。 倒装芯片工艺包括回流焊料凸块并快速冷却焊料凸块，从而将富碳介电层可释放层从晶片上释放出来。

公开(公告)号：US08881379B2

公开(公告)日：2014-11-11

申请号：US13460871

申请日：2012-05-01

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Terence B. Hook ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  William J. Murphy

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Terence B. Hook ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  William J. Murphy

IPC分类号： H05B3/00 ,  H01C1/084 ,  H01C7/10

CPC分类号： H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

摘要翻译： 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

公开(公告)号：US08778737B2

公开(公告)日：2014-07-15

申请号：US13285443

申请日：2011-10-31

申请人： Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles F. Musante ,  BethAnn Rainey ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles F. Musante ,  BethAnn Rainey ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L21/00 ,  H01L29/10

CPC分类号： H01L23/4825 ,  H01L21/6835 ,  H01L21/76819 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L29/1054 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/73251 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/804 ,  H01L2224/80487 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/05552

摘要： Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

摘要翻译： 用于粘结衬底表面，键合衬底组件和用于键合衬底组件的设计结构的方法。 使用器件基板的第一表面形成产品芯片的器件结构。 在产品芯片上形成用于器件结构的互连结构的布线层。 布线层被平坦化。 临时处理晶片可移除地结合到平坦化的布线层。 响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面被结合到最终的手柄基板。 然后将临时手柄晶片从组件中取出。

公开(公告)号：US08631570B2

公开(公告)日：2014-01-21

申请号：US13369414

申请日：2012-02-09

申请人： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

发明人： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC分类号： H01K3/10 ,  H05K3/02 ,  H05K3/10 ,  H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

摘要翻译： 提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。 在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

公开(公告)号：US08440544B2

公开(公告)日：2013-05-14

申请号：US12899127

申请日：2010-10-06

申请人： Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L21/301

CPC分类号： H01L29/06 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/8221 ,  H01L27/0688 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2924/00011 ,  H01L2224/80001

摘要： CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure.

摘要翻译： 具有替代衬底的CMOS结构和制造方法在本文中公开。 该方法包括在临时衬底上形成器件。 该方法还包括移除临时衬底。 所述方法还包括用固定结构将永久电绝缘衬底粘合到所述器件上。

公开(公告)号：US08263497B2

公开(公告)日：2012-09-11

申请号：US12352718

申请日：2009-01-13

申请人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  John M. Cotte ,  Michael F. Lofaro ,  Edmund J. Sprogis ,  James A. Tornello ,  Cornelia K. Tsang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An assembly including a main wafer having a body with a front side and a back side and a plurality of blind electrical vias terminating above the back side, and a handler wafer, is obtained. A step includes exposing the blind electrical vias to various heights on the back side. Another step involves applying a first chemical mechanical polish process to the back side, to open any of the surrounding insulator adjacent the end regions of the cores remaining after the exposing step, and to co-planarize the via conductive cores, the surrounding insulator adjacent the side regions of the cores, and the body of the main wafer. Further steps include etching the back side to produce a uniform standoff height of each of the vias across the back side; depositing a dielectric across the back side; and applying a second chemical mechanical polish process to the back side.

摘要翻译： 获得包括具有前侧和后侧的主体的主晶片和终止于背面的多个盲电通路的组件和处理器晶片。 一个步骤包括将盲电通孔暴露在背面的各种高度上。 另一个步骤涉及将第一化学机械抛光工艺应用于背面，以便打开暴露步骤之后残留的芯的端部附近的任何周围的绝缘体，并且将通孔导电芯，邻近的绝缘体 芯的侧面区域和主晶片的主体。 进一步的步骤包括蚀刻背面以产生穿过背面的每个通路的均匀间隔高度; 在背面沉积电介质; 并向后侧施加第二化学机械抛光工艺。