公开(公告)号：US07253390B2

公开(公告)日：2007-08-07

申请号：US11404831

申请日：2006-04-17

申请人： Warren M. Farnworth ,  Sidney B. Rigg ,  David R. Hembree ,  William M. Hiatt

发明人： Warren M. Farnworth ,  Sidney B. Rigg ,  David R. Hembree ,  William M. Hiatt

IPC分类号： H01L21/00 ,  H01L27/00

CPC分类号： H01L31/0203 ,  B33Y80/00 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/148 ,  H01L2224/48227 ,  H01L2224/48091 ,  H01L2924/00014

摘要： Microelectronic imagers with prefabricated housings and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imager can include a microelectronic die, an image sensor, and an integrated circuit operatively coupled to the integrated circuit. The microelectronic imager also includes an optic unit having an optic member. The microelectronic imager further includes a prefabricated housing having a first mounting site and a second mounting site. The die is seated within the housing at the first mounting site and the optics unit is seated within the housing at the second mounting site in a fixed, preset position in which the optic member is situated at a desired location relative to the image sensor.

摘要翻译： 具有预制外壳的微电子成像器和封装微电子成像器的方法在此公开。 在一个实施例中，微电子成像器可以包括微电子管芯，图像传感器和可操作地耦合到集成电路的集成电路。 微电子成像器还包括具有光学构件的光学单元。 微电子成像器还包括具有第一安装位置和第二安装位置的预制外壳。 模具位于第一安装位置的壳体内，并且光学单元在第二安装位置处置于壳体内的固定的预设位置中，光学构件位于相对于图像传感器的期望位置处。

公开(公告)号：US07199439B2

公开(公告)日：2007-04-03

申请号：US10867352

申请日：2004-06-14

申请人： Warren M. Farnworth ,  Sidney B. Rigg ,  William M. Hiatt ,  Kyle K. Kirby ,  Peter A. Benson ,  James M. Wark ,  Alan G. Wood ,  David R. Hembree ,  Salman Akram ,  Charles M. Watkins

发明人： Warren M. Farnworth ,  Sidney B. Rigg ,  William M. Hiatt ,  Kyle K. Kirby ,  Peter A. Benson ,  James M. Wark ,  Alan G. Wood ,  David R. Hembree ,  Salman Akram ,  Charles M. Watkins

IPC分类号： H01L31/0203

CPC分类号： H01L27/14618 ,  H01L23/481 ,  H01L24/48 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.

摘要翻译： 本文公开了微电子成像器和用于封装微电子成像器的方法。 在一个实施例中，微电子成像单元可以包括微电子管芯，图像传感器，电耦合到图像传感器的集成电路以及电耦合到集成电路的接合焊盘。 导电晶片互连延伸穿过管芯并且与焊盘接触。 互连可以包括完全延伸穿过基底的通道和具有至少部分地设置在通道中的导电填充材料的接合垫。 导电支撑构件由接合垫承载和突出。 图像传感器上的盖连接到支撑构件。

公开(公告)号：US07064010B2

公开(公告)日：2006-06-20

申请号：US10690417

申请日：2003-10-20

申请人： Warren M. Farnworth ,  Kyle K. Kirby ,  William M. Hiatt

发明人： Warren M. Farnworth ,  Kyle K. Kirby ,  William M. Hiatt

IPC分类号： H01L21/463 ,  H01L21/465 ,  H01L21/82

CPC分类号： H01L21/463 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3185 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/03

摘要： Separating and coating semiconductor dice at the wafer level to form individual chip-scale packages. In one embodiment, channels are formed in the active surface of a wafer to expose side surfaces of semiconductor dice. The surfaces of the channels are then etched to remove defects resulting from cutting. A first protective coating is deposited to seal the wafer active surface and the exposed side surfaces of each semiconductor die. Finally, the wafer is singulated along the channels to provide a plurality of individual chip-scale packages. Alternatively, material is removed from the back side of the wafer to expose the channels, and a second protective coating is applied to provide completely sealed chip-scale packages. Portions of the first protective coating may also be formed to project from the channels to anchor the second protective coating in place. In another embodiment, the first protective coating is formed without forming channels in the active surface of the wafer, and then channels are formed in the back side of the wafer.

摘要翻译： 在晶圆级别分离和涂覆半导体晶片以形成单个芯片级封装。 在一个实施例中，在晶片的有源表面中形成沟道以露出半导体晶片的侧表面。 然后蚀刻通道的表面以除去由切割引起的缺陷。 沉积第一保护涂层以密封每个半导体管芯的晶片有源表面和暴露的侧表面。 最后，晶片沿通道分割，以提供多个独立的芯片级封装。 或者，从晶片的背面去除材料以暴露通道，并且施加第二保护涂层以提供完全密封的芯片级封装。 第一保护涂层的部分也可以形成为从通道突出以将第二保护涂层锚固到位。 在另一个实施例中，形成第一保护涂层而不在晶片的有效表面中形成通道，然后在晶片的背面形成通道。

公开(公告)号：US07060526B2

公开(公告)日：2006-06-13

申请号：US10730333

申请日：2003-12-08

申请人： Warren M. Farnworth ,  Alan G. Wood ,  William M. Hiatt ,  James M. Wark ,  David R. Hembree ,  Kyle K. Kirby ,  Pete A. Benson

发明人： Warren M. Farnworth ,  Alan G. Wood ,  William M. Hiatt ,  James M. Wark ,  David R. Hembree ,  Kyle K. Kirby ,  Pete A. Benson

IPC分类号： H01L21/44

CPC分类号： H01L21/561 ,  B33Y70/00 ,  B33Y80/00 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.

摘要翻译： 半导体部件包括基模和层叠在基模上的二次模。 基模具包括形成用于部件的内部信号传输系统的导电通孔，并允许二次管芯的电路侧接合到基座的后侧。 该组件还包括与导电通孔电连通的基座芯片的电路侧上的端子触点阵列。 该组件还可以包括在基模的背侧上的密封剂，其基本上封装次模，以及在用作保护层的基模的电路侧上的聚合物层，用于形成的用于固化的模板 终端接触。 一种用于制造该部件的方法包括将单个二次骰子接合到基底晶片上的基底骰子上，或将次晶片接合到基底晶片，或将单个二次骰子接合到单个基体骰子的步骤。

公开(公告)号：US06841883B1

公开(公告)日：2005-01-11

申请号：US10403937

申请日：2003-03-31

申请人： Warren M. Farnworth ,  Alan G. Wood ,  William M. Hiatt ,  James M. Wark ,  David R. Hembree ,  Kyle K. Kirby ,  Pete A. Benson

发明人： Warren M. Farnworth ,  Alan G. Wood ,  William M. Hiatt ,  James M. Wark ,  David R. Hembree ,  Kyle K. Kirby ,  Pete A. Benson

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L21/98 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L29/40

CPC分类号： H01L21/561 ,  B33Y70/00 ,  B33Y80/00 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.

摘要翻译： 半导体部件包括基模和层叠在基模上的二次模。 基模具包括形成用于部件的内部信号传输系统的导电通孔，并允许二次管芯的电路侧接合到基座的后侧。 该组件还包括与导电通孔电连通的基座芯片的电路侧上的端子触点阵列。 该组件还可以包括在基模的背侧上的密封剂，其基本上封装次模，以及在用作保护层的基模的电路侧上的聚合物层，用于形成的用于固化的模板 终端接触。 一种用于制造该部件的方法包括将单个二次骰子接合到基底晶片上的基底骰子上，或将次晶片接合到基底晶片，或将单个二次骰子接合到单个基体骰子的步骤。

公开(公告)号：US09337162B2

公开(公告)日：2016-05-10

申请号：US13613047

申请日：2012-09-13

申请人： William M. Hiatt ,  Warren M. Farnworth

发明人： William M. Hiatt ,  Warren M. Farnworth

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05557 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11902 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/13155 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2924/00014

摘要： An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

公开(公告)号：US08637994B2

公开(公告)日：2014-01-28

申请号：US13605761

申请日：2012-09-06

申请人： Warren M. Farnworth ,  Rick C. Lake ,  William M. Hiatt

发明人： Warren M. Farnworth ,  Rick C. Lake ,  William M. Hiatt

IPC分类号： H01L21/441 ,  H01L29/40 ,  B23K35/14

CPC分类号： B23K1/20 ,  B23K1/0016 ,  B23K35/22 ,  H01L29/40 ,  H01L2224/05001 ,  H01L2224/11 ,  Y10T428/12493 ,  Y10T428/12708 ,  Y10T428/12889 ,  Y10T428/12896 ,  Y10T428/12903

摘要： Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a target location of a microfeature workpiece, with the volume of material including at least a first metallic constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the microfeature workpiece to alloy the first metallic constituent and a second metallic constituent so that the second metallic constituent is distributed generally throughout the volume of material. In further particular embodiments, the second metallic constituent can be drawn from an adjacent structure, for example, a bond pad or the wall of a via in which the volume of material is positioned.

摘要翻译： 公开了具有合金导电结构的微型工件和相关方法。 根据一个实施例的方法包括将一定体积的材料施加到微特征工件的目标位置，其中材料的体积至少包括第一金属成分。 该方法还可以包括升高材料体积的温度，同时将材料的体积施加到微特征工件以使第一金属构件和第二金属构件合金，使得第二金属构件通常分布在整个体积的材料中。 在另外的特定实施例中，第二金属构件可以从相邻的结构（例如，接合垫或通孔的壁）中被拉出，在其中材料的体积被定位在其中。

公开(公告)号：US07683458B2

公开(公告)日：2010-03-23

申请号：US11924781

申请日：2007-10-26

申请人： Salman Akram ,  Charles M. Watkins ,  William M. Hiatt ,  David R. Hembree ,  James M. Wark ,  Warren M. Farnworth ,  Mark E. Tuttle ,  Sidney B. Rigg ,  Steven D. Oliver ,  Kyle K. Kirby ,  Alan G. Wood ,  Lu Velicky

发明人： Salman Akram ,  Charles M. Watkins ,  William M. Hiatt ,  David R. Hembree ,  James M. Wark ,  Warren M. Farnworth ,  Mark E. Tuttle ,  Sidney B. Rigg ,  Steven D. Oliver ,  Kyle K. Kirby ,  Alan G. Wood ,  Lu Velicky

IPC分类号： H01L23/485

CPC分类号： H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

摘要翻译： 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

公开(公告)号：US20090191701A1

公开(公告)日：2009-07-30

申请号：US12419029

申请日：2009-04-06

申请人： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

发明人： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

摘要翻译： 本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。 在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。 衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。 该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。 该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。 该方法然后包括用导电材料填充通道。

公开(公告)号：US07488899B2

公开(公告)日：2009-02-10

申请号：US11151925

申请日：2005-06-14

申请人： Kyle K. Kirby ,  Warren M. Farnworth ,  James M. Wark ,  William M. Hiatt ,  David R. Hembree ,  Alan G. Wood

发明人： Kyle K. Kirby ,  Warren M. Farnworth ,  James M. Wark ,  William M. Hiatt ,  David R. Hembree ,  Alan G. Wood

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： G01R1/0735 ,  G01R1/07314 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01R12/714 ,  H01R13/24 ,  H01R2201/20 ,  H05K3/326 ,  H05K7/1069 ,  H05K2201/0314 ,  H05K2201/09036 ,  H05K2201/10378 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599

摘要： A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.

摘要翻译： 提供了柔性接触销组件和接触器卡系统。 柔性接触销组件包括由基板的一部分形成的接触销，其中触头销顺从地保持通过柔性联接结构悬挂在基板内。 衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。 接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。 在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。