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公开(公告)号：US20180233398A1
公开(公告)日：2018-08-16
申请号：US15893458
申请日：2018-02-09
IPC分类号： H01L21/768 , H01L29/417 , H01L29/66 , H01L21/311 , H01L21/67
CPC分类号： H01L21/7682 , H01L21/02175 , H01L21/02274 , H01L21/0228 , H01L21/31122 , H01L21/67069 , H01L21/67259 , H01L21/76897 , H01L29/41775 , H01L29/41791 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785
摘要： Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an H2-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% H2. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.
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公开(公告)号：US10002787B2
公开(公告)日：2018-06-19
申请号：US15408291
申请日：2017-01-17
IPC分类号： H01L21/768 , H01L23/528 , H01L21/56 , H01L21/02 , H01L21/311 , H01L27/11551 , H01L27/11578 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76816 , H01L21/02126 , H01L21/02167 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/0228 , H01L21/31111 , H01L21/31116 , H01L21/56 , H01L21/76834 , H01L23/3157 , H01L27/11575 , H01L27/11582
摘要： Methods and apparatuses for depositing an encapsulation layer over a staircase structure during fabrication of a 3D NAND structure to prevent degradation of an oxide-oxide interface and to prevent punchthrough of a wordline are provided. The encapsulation layer is a carbon-containing conformal film deposited over a staircase structure of alternating oxide and nitride layers prior to depositing oxide over the staircase structure.
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公开(公告)号：US20180108529A1
公开(公告)日：2018-04-19
申请号：US15593187
申请日：2017-05-11
发明人： William T. Lee , Bart J. van Schravendijk , David Charles Smith , Michal Danek , Patrick A. Van Cleemput , Ramesh Chandrasekharan
IPC分类号： H01L21/28 , H01L21/02 , H01J37/32 , H01L29/51 , G02F1/1335
CPC分类号： H01L21/28202 , G02F1/133502 , H01J37/3244 , H01J37/32788 , H01L21/02175 , H01L21/022 , H01L21/28211 , H01L29/513
摘要： Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO2/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.
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公开(公告)号：US20170323786A1
公开(公告)日：2017-11-09
申请号：US15654186
申请日：2017-07-19
发明人： Hu Kang , Shankar Swaminathan , Jun Qian , Wanki Kim , Dennis Hausmann , Bart J. van Schravendijk , Adrien LaVoie
IPC分类号： H01L21/02 , C23C16/34 , H01L21/762 , H01L21/67 , C23C16/04 , C23C16/56 , C23C16/455 , C23C16/40 , H01L21/768 , H01L21/285
CPC分类号： H01L21/02274 , C23C16/045 , C23C16/345 , C23C16/402 , C23C16/45523 , C23C16/4554 , C23C16/56 , H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02219 , H01L21/0228 , H01L21/28562 , H01L21/67201 , H01L21/76224 , H01L21/76229 , H01L21/76826 , H01L21/76837
摘要： Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.
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公开(公告)号：US09379210B2
公开(公告)日：2016-06-28
申请号：US14883457
申请日：2015-10-14
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L21/762 , H01L21/28 , H01L21/311
CPC分类号： H01L29/66545 , H01L21/02175 , H01L21/02178 , H01L21/02271 , H01L21/02274 , H01L21/02277 , H01L21/0228 , H01L21/28008 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/762 , H01L21/76224 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L29/517 , H01L29/66553 , H01L29/78 , H01L29/7845
摘要： Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process flow is used, which may involve the deposition and removal of a sacrificial pre-metal dielectric material before a particular contact etch stop layer is formed. An auxiliary contact etch stop layer may be used in addition to a primary etch stop layer that is deposited previously. In certain cases the contact etch stop layer is a metal-containing material such as a nitride or an oxide. The contact etch stop layer may be deposited through a cyclic vapor deposition in some embodiments. The process flows disclosed herein provide improved protection against over-etching gate stacks, thereby minimizing gate-to-contact leakage. Further, the disclosed process flows result in wider flexibility in terms of materials and deposition conditions used for forming various dielectric materials, thereby minimizing parasitic capacitance.
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公开(公告)号：US20160071953A1
公开(公告)日：2016-03-10
申请号：US14883457
申请日：2015-10-14
IPC分类号： H01L29/66 , H01L21/311 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/02175 , H01L21/02178 , H01L21/02271 , H01L21/02274 , H01L21/02277 , H01L21/0228 , H01L21/28008 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/762 , H01L21/76224 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L29/517 , H01L29/66553 , H01L29/78 , H01L29/7845
摘要： Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process flow is used, which may involve the deposition and removal of a sacrificial pre-metal dielectric material before a particular contact etch stop layer is formed. An auxiliary contact etch stop layer may be used in addition to a primary etch stop layer that is deposited previously. In certain cases the contact etch stop layer is a metal-containing material such as a nitride or an oxide. The contact etch stop layer may be deposited through a cyclic vapor deposition in some embodiments. The process flows disclosed herein provide improved protection against over-etching gate stacks, thereby minimizing gate-to-contact leakage. Further, the disclosed process flows result in wider flexibility in terms of materials and deposition conditions used for forming various dielectric materials, thereby minimizing parasitic capacitance.
摘要翻译： 本文的各种实施例涉及在形成栅极和触点的上下文中形成接触蚀刻停止层。 在某些实施例中，使用新的工艺流程，其可以涉及在形成特定的接触蚀刻停止层之前沉积和去除牺牲预金属介电材料。 除了先前沉积的原始蚀刻停止层之外，还可以使用辅助接触蚀刻停止层。 在某些情况下，接触蚀刻停止层是含金属的材料，例如氮化物或氧化物。 在一些实施方案中，接触蚀刻停止层可通过环状气相沉积沉积。 本文公开的工艺流程提供了改进的防蚀蚀栅极堆叠的保护，从而最小化了栅极 - 接触泄漏。 此外，所公开的工艺流程在用于形成各种介电材料的材料和沉积条件方面产生更大的灵活性，从而最小化寄生电容。
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公开(公告)号：US20160056071A1
公开(公告)日：2016-02-25
申请号：US14464071
申请日：2014-08-20
发明人： Nerissa Sue Draeger , Kaihan Abidi Ashtiani , Deenesh Padhi , Derek B. Wong , Bart J. van Schravendijk , George Andrew Antonelli , Artur Kolics , Lie Zhao , Patrick A. van Cleemput
IPC分类号： H01L21/768 , C23C16/46 , C23C16/52
CPC分类号： H01L21/76826 , C23C16/045 , C23C16/401 , C23C16/56 , H01L21/3105 , H01L21/76814 , H01L21/76825 , H01L21/76831 , H01L21/76843 , H01L21/76876 , H01L23/53238 , H01L23/5329
摘要： Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods involve exposing a substrate having an exposed porous dielectric film thereon to a vapor phase dielectric precursor under conditions such that a flowable dielectric material selectively deposits in the pores of the porous dielectric material. The pores can be filled with the deposited flowable dielectric material without depositing a continuous film on any exposed metal surface.
摘要翻译： 本文公开的方法和装置的实施涉及使用可流动电介质材料的多孔绝缘膜的孔密封。 所述方法包括将其上具有暴露的多孔介电膜的衬底暴露于气相电介质前体，使得可流动介电材料选择性地沉积在多孔介电材料的孔中。 可以用沉积的可流动电介质材料填充孔，而不在任何暴露的金属表面上沉积连续的膜。
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公开(公告)号：US12040181B2
公开(公告)日：2024-07-16
申请号：US17594816
申请日：2019-07-03
发明人： Chan Myae Myae Soe , Chloe Baldasseroni , Shiva Sharan Bhandari , Pulkit Agarwal , Adrien LaVoie , Bart J. van Schravendijk
IPC分类号： H01L21/02 , C23C16/40 , C23C16/455 , C23C16/52
CPC分类号： H01L21/0228 , C23C16/401 , C23C16/45536 , C23C16/45544 , C23C16/52 , H01L21/02164 , H01L21/02211 , H01L21/02274
摘要： Methods and apparatuses for depositing thin films using long and short conversion times during alternating cycles of atomic layer deposition (ALD) are provided herein. Embodiments involve alternating conversion duration of an ALD cycle in one or more cycles of a multi-cycle ALD process. Some embodiments involve modulation of dose, purge, pressure, plasma power or plasma energy in two or more ALD cycles.
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公开(公告)号：US11784047B2
公开(公告)日：2023-10-10
申请号：US17302044
申请日：2021-04-22
发明人： David Charles Smith , Richard Wise , Arpan Pravin Mahorowala , Patrick A. van Cleemput , Bart J. van Schravendijk
IPC分类号： H01L21/033 , H01L21/3213 , C23C16/455 , H01L21/311 , C23C16/40 , H01J37/32 , C23C16/56 , H01L21/02 , H01L21/027 , H01L21/67
CPC分类号： H01L21/0332 , C23C16/407 , C23C16/45542 , C23C16/45553 , C23C16/56 , H01J37/32091 , H01L21/0228 , H01L21/0271 , H01L21/02175 , H01L21/02274 , H01L21/0337 , H01L21/31111 , H01L21/31122 , H01L21/31144 , H01L21/32137 , H01L21/32139 , H01L21/67069 , H01J37/32862 , H01J2237/3321 , H01J2237/3341 , H01J2237/3342
摘要： Thin tin oxide films can be used in semiconductor device manufacturing. In one implementation, a method of processing a semiconductor substrate includes: providing a semiconductor substrate having a plurality of protruding features residing on an etch stop layer material, and an exposed tin oxide layer in contact with both the protruding features and the etch stop layer material, where the tin oxide layer covers both sidewalls and horizontal surfaces of the protruding features; and then completely removing the tin oxide layer from horizontal surfaces of the semiconductor substrate without completely removing the tin oxide layer residing at the sidewalls of the protruding features. Next, the protruding features can be removed without completely removing the tin oxide layer that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers.
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公开(公告)号：US20220068636A1
公开(公告)日：2022-03-03
申请号：US17310132
申请日：2020-01-15
IPC分类号： H01L21/02 , H01L27/11551
摘要： Films that can be useful in large area gap fill applications, such as in the formation of advanced 3D NAND devices, involve processing a semiconductor substrate by depositing on a patterned semiconductor substrate a doped silicon oxide film, the film having a thickness of at least 5 gm, and annealing the doped silicon oxide film to a temperature above the film glass transition temperature. In some embodiments, reflow of the film may occur. The composition and processing conditions of the doped silicon oxide film may be tailored so that the film exhibits substantially zero as-deposited stress, substantially zero stress shift post-anneal, and substantially zero shrinkage post-anneal.
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