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    Selectabe-tap equalizer
    41.
    发明授权
    Selectabe-tap equalizer 有权

    公开(公告)号：US10355888B2

    公开(公告)日：2019-07-16

    申请号：US16126121

    申请日：2018-09-10

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

    IPC: H04L25/03 ,  H04L7/033 ,  H04L7/00 ,  H04B1/10

    Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

    Clock generation for timing communications with ranks of memory devices
    45.
    发明授权
    Clock generation for timing communications with ranks of memory devices 有权

    公开(公告)号：US10162772B2

    公开(公告)日：2018-12-25

    申请号：US15424714

    申请日：2017-02-03

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

    IPC: G06F1/04 ,  G06F1/10 ,  G06F13/16 ,  G11C7/22 ,  G06F1/06 ,  G06F1/08 ,  H04L7/033 ,  G11C7/04

    Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

    Selectable-tap equalizer
    46.
    发明授权
    Selectable-tap equalizer 有权

    公开(公告)号：US10103907B2

    公开(公告)日：2018-10-16

    申请号：US15715032

    申请日：2017-09-25

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

    IPC: H04L25/03 ,  H04B1/10 ,  H04L7/033 ,  H04L7/00

    Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

    INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO DETERMINE SETTINGS FOR AN INJECTION-LOCKED OSCILLATOR
    49.
    发明申请
    INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO DETERMINE SETTINGS FOR AN INJECTION-LOCKED OSCILLATOR 审中-公开

    公开(公告)号：US20180013438A1

    公开(公告)日：2018-01-11

    申请号：US15632063

    申请日：2017-06-23

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Masum Hossain

    IPC: H03L7/24 ,  H03L1/00 ,  H03K3/03 ,  H03L7/06

    CPC classification number: H03L7/24 ,  H03K3/0307 ,  H03K3/0315 ,  H03L1/00 ,  H03L7/06

    Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more

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