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公开(公告)号：US20160037620A1
公开(公告)日：2016-02-04
申请号：US14668804
申请日：2015-03-25
发明人： Myung Sam KANG , Young Gwan KO , Tae Hong MIN , Jung Han LEE
CPC分类号： H05K1/0204 , H01L23/3677 , H01L23/49827 , H05K1/0206 , H05K3/4602 , H05K2201/10416
摘要： There is provided a printed circuit board including: a core layer having a cavity formed therein; a heat radiation body included in the cavity; an insulating layer provided on an upper surface and a lower surface of the core layer; and a heat dissipating via penetrating through the insulating layer to be in contact with the heat radiation body and dissipating heat externally, wherein the heat radiation body includes an insulating plate, a first metal block formed on an upper surface of the insulating plate, and a second metal block formed on a lower surface of the insulating plate.
摘要翻译： 提供了一种印刷电路板，包括：其中形成有腔的芯层; 包括在腔中的散热体; 设置在所述芯层的上表面和下表面上的绝缘层; 以及通过贯穿所述绝缘层与所述散热体接触并从外部散热的散热部，其中所述散热体包括绝缘板，形成在所述绝缘板的上表面上的第一金属块，以及 第二金属块形成在绝缘板的下表面上。
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42.发明申请CARRIER SUBSTRATE AND METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD USING THE SAME 审中-公开载体基板和使用其制造印刷电路板的方法公开(公告)号：US20160037619A1
公开(公告)日：2016-02-04
申请号：US14734933
申请日：2015-06-09
发明人： Yong Ho BAEK , Young Gwan KO , Jae Hoon CHOI , Il Jong SEO , Sung Uk LEE , Eung Suek LEE
CPC分类号： H05K3/4682 , H05K3/0097 , H05K2203/0152 , H05K2203/1536
摘要： There are provided a carrier substrate including: a first metal layer; a barrier layer formed on one surface of the first carrier metal layer; and a second metal layer formed on one surface of the barrier layer, and a method of manufacturing a printed circuit board using the same.
摘要翻译： 提供了一种载体基板，包括：第一金属层; 形成在所述第一载体金属层的一个表面上的阻挡层; 以及形成在阻挡层的一个表面上的第二金属层，以及使用其形成印刷电路板的方法。
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公开(公告)号：US20160007449A1
公开(公告)日：2016-01-07
申请号：US14754363
申请日：2015-06-29
发明人： Joon Sung KIM , Yong Ho BAEK , Jung Hyun CHO , Eung Suek LEE , Jae Hoon CHOI , Young Gwan KO
CPC分类号： H01L23/49827 , H01L21/4846 , H01L23/13 , H01L23/5389 , H01L24/25 , H01L24/82 , H01L2224/04105 , H01L2224/19 , H01L2224/2518 , H01L2224/32225 , H01L2224/83005 , H01L2224/92144 , H01L2924/14 , H01L2924/15153 , H01L2924/3511 , H05K1/0298 , H05K1/185 , H05K3/10 , H05K3/30 , H05K3/305 , H05K3/4602 , H05K3/4644 , H05K2201/09227 , H05K2203/1469 , H05K2203/167
摘要： Disclosed herein is a chip embedded substrate including: an insulating layer having outer layer circuit patterns provided on any one of an upper surface and a lower surface thereof; a chip embedded in the insulating layer; and internal circuit patterns included in the insulating layer and disposed between a height of a top surface of the chip and a height of a bottom surface thereof.
摘要翻译： 本文公开了一种芯片嵌入式基板，包括：绝缘层，其具有设置在其上表面和下表面中的任一个上的外层电路图案; 嵌入绝缘层中的芯片; 以及包括在绝缘层中并且设置在芯片的顶表面的高度和其底表面的高度之间的内部电路图案。
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公开(公告)号：US20140000952A1
公开(公告)日：2014-01-02
申请号：US13921128
申请日：2013-06-18
发明人： Young Gwan KO
IPC分类号： H05K1/11
CPC分类号： H05K1/114 , H05K3/0097 , H05K3/107 , H05K3/4007 , H05K3/4682 , H05K2201/0352 , H05K2201/0367 , H05K2203/1536
摘要： Disclosed is a printed circuit board, which includes an insulating member having a circuit pattern embedded in one surface thereof, a bump pad formed in the insulating member so as to be connected to the circuit pattern and protruding from an outer surface of the insulating member, a build-up layer formed on one surface of the insulating member and including a build-up insulating layer and a circuit layer formed in the build-up insulating layer and having a via connected to the circuit pattern, and a solder resist layer formed on the build-up layer. A method of fabricating the printed circuit board is also provided. The printed circuit board is fabricated using a build-up process and the outermost circuit layer thereof is formed to have an embedded structure using an imprinting process, thus minimizing the separation of the circuit layer and reducing the lead time and the fabrication cost.
摘要翻译： 公开了一种印刷电路板，其包括具有嵌入其一个表面中的电路图案的绝缘构件，形成在所述绝缘构件中以与所述电路图案连接并从所述绝缘构件的外表面突出的凸块焊盘， 形成在所述绝缘构件的一个表面上并包括积聚绝缘层和形成在所述积层绝缘层中并且具有连接到所述电路图案的通孔的电路层的堆积层，以及形成在所述绝缘层上的阻焊层 积层。 还提供了制造印刷电路板的方法。 印刷电路板使用积聚工艺制造，并且其最外面的电路层被形成为具有使用压印工艺的嵌入式结构，从而最小化电路层的分离并减少了交货时间和制造成本。
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公开(公告)号：US20190131270A1
公开(公告)日：2019-05-02
申请号：US15988647
申请日：2018-05-24
发明人： Jeong Ho LEE , Bong Ju CHO , Young Gwan KO , Jin Su KIM , Shang Hoon SEO , Jeong Il LEE
IPC分类号： H01L23/00 , H01L21/48 , H01L21/56 , H01L23/498 , H01L23/31
摘要： A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.
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公开(公告)号：US20190131242A1
公开(公告)日：2019-05-02
申请号：US15981651
申请日：2018-05-16
发明人： Jeong Ho LEE , Myung Sam KANG , Young Gwan KO , Shang Hoon SEO , Jin Su KIM
IPC分类号： H01L23/538 , H01L23/498 , H01L23/31 , H01L25/065
摘要： A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; a first encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; an electronic component disposed on the other surface of the frame opposing one surface of the frame in which the semiconductor chip is disposed; a second encapsulant covering at least portions of the electronic component; and a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer, wherein the connection pads and the electronic component are electrically connected to each other through the wiring layers and the redistribution layer.
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公开(公告)号：US20190013256A1
公开(公告)日：2019-01-10
申请号：US15966723
申请日：2018-04-30
发明人： Han Ul LEE , Jin Su KIM , Young Gwan KO
IPC分类号： H01L23/31 , H01L23/00 , H01L23/498 , H01L23/538 , H01L21/3105 , H01L21/56 , H01L21/48 , H01L21/683 , H01L25/18
CPC分类号： H01L23/3128 , H01L21/31058 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3135 , H01L23/49816 , H01L23/5383 , H01L23/5386 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/82 , H01L25/0655 , H01L25/18 , H01L2221/68345 , H01L2224/02377 , H01L2224/024 , H01L2224/0401 , H01L2224/05008 , H01L2224/0501 , H01L2224/05124 , H01L2224/05569 , H01L2224/05624 , H01L2224/06133 , H01L2224/11334 , H01L2224/13024 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2924/143 , H01L2924/1434 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2924/0665 , H01L2924/00014
摘要： A semiconductor device includes: a chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the chip; a connection member disposed on the active surface of the chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an under bump metallurgy (UBM) layer at least partially embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad partially embedded in the passivation layer and a UVM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other. A portion of a side surface of the UBM pad is exposed through an opening formed in the passivation layer and the opening surrounds the UBM pad.
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公开(公告)号：US20180342449A1
公开(公告)日：2018-11-29
申请号：US16035192
申请日：2018-07-13
发明人： Da Hee KIM , Young Gwan KO , Sung Won JEONG
IPC分类号： H01L23/498 , H01L23/00 , H01L23/433 , H01L23/31
CPC分类号： H01L23/49822 , H01L23/3114 , H01L23/3121 , H01L23/3128 , H01L23/36 , H01L23/4334 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/09 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/1035 , H01L2225/1041 , H01L2225/1094 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/37001 , H01L2924/00012 , H01L2924/00
摘要： A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a second connection member disposed on the first connection member and the active surface of the semiconductor chip; and a heat dissipation layer embedded in the encapsulant so that one surface thereof is exposed. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip.
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公开(公告)号：US20180233433A1
公开(公告)日：2018-08-16
申请号：US15948535
申请日：2018-04-09
发明人： Yoon Su KIM , Seung Min BAEK , Young Gwan KO
IPC分类号： H01L23/485 , H01L23/498 , H01L23/00 , H01L21/48 , H01L23/482 , H01L25/10
CPC分类号： H01L23/485 , H01L21/4857 , H01L21/486 , H01L23/3128 , H01L23/4827 , H01L23/49816 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/18162 , H01L2924/3025 , H01L2924/37001 , H01L2924/014 , H01L2924/00014
摘要： A fan-out semiconductor package includes a semiconductor chip including a body and an electrode pad disposed on the body, a metal layer disposed on the electrode pad of the semiconductor chip, and a interconnection member including an insulating layer disposed on one side of the semiconductor chip, a via hole penetrating through the insulating layer and exposing at least a portion of a surface of the metal layer, a seed layer disposed on the surface of the metal layer exposed by the via hole and a wall of the via hole, and a conductor layer disposed on the seed layer.
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公开(公告)号：US20180233432A1
公开(公告)日：2018-08-16
申请号：US15955178
申请日：2018-04-17
发明人： Han KIM , Young Gwan KO , Kang Heon HUR , Kyung Moon JUNG , Sung Han KIM
IPC分类号： H01L23/48 , H01L23/31 , H01L23/00 , H01L23/498 , H01L23/538
摘要： An electronic component package may include: a redistribution layer including a first insulating layer, a first conductive pattern disposed on the first insulating layer, and a first via connected to the first conductive pattern while penetrating through the first insulating layer; an electronic component disposed on the redistribution layer; and an encapsulant encapsulating the electronic component. The first via has a horizontal cross-sectional shape in which a distance between first and second edge points of the first via in a first direction passing through the center of the first via and the first and second edge points thereof is shorter than that between third and fourth edge points of the first via in a second direction perpendicular to the first direction and passing through the center of the first via and the third and fourth points thereof.
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