公开(公告)号：US07432586B2

公开(公告)日：2008-10-07

申请号：US10870927

申请日：2004-06-21

Applicant: Sam Ziqun Zhao ,  Reza-ur Rahman Khan

Inventor： Sam Ziqun Zhao ,  Reza-ur Rahman Khan

IPC: H01L23/02

CPC classification number: H01L23/24 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16315 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An apparatus and method for enhancing thermal performance and electromagnetic interference (EMI) shielding in die-up array integrated circuit (IC) device packages is presented. A die-up array package includes an IC die mounted to a first stiffener surface. The package further includes a cap body having first and second surfaces. A first portion of the second surface has a cavity formed therein, and a planar second portion of the second surface is coupled to the first stiffener surface. The package further includes a substrate having a first surface coupled to a second stiffener surface. A plurality of contact pads on the first substrate surface are electrically connected to an array of electrically conductive terminals on a second substrate surface. The stiffener and cap body form a die enclosure that dissipates heat during operation of the IC die, and shields EMI emanating from and radiating toward the IC die.

Abstract translation: 提出了一种用于增强压电阵列集成电路（IC）器件封装中的热性能和电磁干扰（EMI）屏蔽的装置和方法。 一种放电阵列封装包括安装在第一加强件表面上的IC管芯。 所述包装还包括具有第一表面和第二表面的盖体。 第二表面的第一部分具有形成在其中的空腔，并且第二表面的平面第二部分联接到第一加强件表面。 该封装还包括具有耦合到第二加强件表面的第一表面的基板。 第一衬底表面上的多个接触焊盘电连接到第二衬底表面上的导电端子阵列。 加强件和盖体形成了在IC管芯工作期间散热的管芯外壳，并且屏蔽从IC管芯发出并朝向IC管芯辐射的EMI。

公开(公告)号：US20070267734A1

公开(公告)日：2007-11-22

申请号：US11480579

申请日：2006-07-05

Applicant: Sam Ziqun Zhao ,  Rezaur Rahman Khan

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/24

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/166 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages are described. A die-up or die-down package includes an IC die, a die attach pad, a heat spreader cap coupled to the die attach pad defining a cavity, and one or more peripheral rows of leads surrounding the die attach pad. The leads do not protrude substantially from the footprint of the encasing structure. The die attach pad and the heat spreader cap defines an encasing structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The encasing structure also dissipates heat generated by the IC die during operation.

Abstract translation: 描述了用于改善集成电路（IC）封装中的热性能和电磁干扰（EMI）屏蔽的方法和装置。 芯片封装或芯片封装包括IC芯片，芯片连接焊盘，耦合到限定空腔的管芯连接焊盘的散热器帽以及围绕焊盘附接焊盘的一个或多个外围引线行。 引线不会从封装结构的覆盖区基本上突出。 管芯附接垫和散热器帽限定了基本上封装IC管芯的封装结构，并且屏蔽从IC管芯发出并朝向IC管芯辐射的EMI。 封装结构还在运行期间消散IC芯片产生的热量。

公开(公告)号：US07245500B2

公开(公告)日：2007-07-17

申请号：US10284371

申请日：2002-10-31

Applicant: Reza-ur Rahman Khan ,  Sam Ziqun Zhao

Inventor： Reza-ur Rahman Khan ,  Sam Ziqun Zhao

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/10

CPC classification number: H01L23/49833 ,  H01L23/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/49109 ,  H01L2224/83385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted on a first surface of a stiffener. A first surface of a substrate is attached to a second surface of the stiffener that is opposed to the first surface of the stiffener. A bond pad of the IC die is coupled to a contact pad on the first surface of the substrate with a wire bond. The wire bond is coupled over a recessed step region in the first surface of the stiffener and through a through-pattern in the stiffener that has an edge adjacent to the recessed step region. The through-pattern in the stiffener is one of an opening through the stiffener, a recessed portion in an edge of the stiffener, or other through-pattern.

Abstract translation: 描述了电，热和机械增强的球栅阵列（BGA）封装。 IC模具安装在加强件的第一表面上。 衬底的第一表面附接到与加强件的第一表面相对的加强件的第二表面。 IC芯片的接合焊盘通过引线接合耦合到衬底的第一表面上的接触焊盘。 引线接合耦合在加强件的第一表面中的凹陷阶梯区域上，并且通过加强件中的贯穿图案耦合，所述贯穿图案具有与凹陷步骤区域相邻的边缘。 加强件中的贯穿图案是通过加强件的开口，加强件的边缘中的凹陷部分或其它贯穿图案之一。

公开(公告)号：US07241645B2

公开(公告)日：2007-07-10

申请号：US10932278

申请日：2004-09-02

Applicant: Sam Ziqun Zhao ,  Reza-ur Rahman Khan

Inventor： Sam Ziqun Zhao ,  Reza-ur Rahman Khan

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/10 ,  H01L23/34 ,  H01L23/498

CPC classification number: H01L24/49 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/32188 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/48624 ,  H01L2224/4911 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.

Abstract translation: 描述了电，热和机械增强的球栅阵列（BGA）封装。 IC模具安装到第一加强件的第一表面。 第一加强件的第二表面的外围边缘部分附接到第二加强件的第一表面，以覆盖通过在第一表面处开口的第二加强件的开口和第二加强件的第二表面。 第二加强件的第二表面附接到在基板的第一表面上具有多个接触焊盘的基本平坦的基板的第一表面。 多个接触焊盘通过衬底电连接到衬底的第二表面上的多个焊球焊盘。

公开(公告)号：US06989593B2

公开(公告)日：2006-01-24

申请号：US10201309

申请日：2002-07-24

Applicant: Reza-ur Rahman Khan ,  Sam Ziqun Zhao ,  Brent Bacher

Inventor： Reza-ur Rahman Khan ,  Sam Ziqun Zhao ,  Brent Bacher

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L23/34 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface. In another aspect, wire bond openings in the stiffener are bridged by one or more studs.

公开(公告)号：US06876553B2

公开(公告)日：2005-04-05

申请号：US10101751

申请日：2002-03-21

Applicant: Sam Ziqun Zhao ,  Reza-ur Rahman Khan ,  Imtiaz Chaudhry

Inventor： Sam Ziqun Zhao ,  Reza-ur Rahman Khan ,  Imtiaz Chaudhry

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H01L24/48 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: An electrically and thermally enhanced die-up ball grid array (BGA) package is described. An integrated circuit (IC) package includes a first substrate, a second substrate, and a stiffener. A surface of the first substrate is attached to a first surface of the stiffener. A surface of the second substrate is attached to a second surface of the stiffener. An IC die may be attached to a second surface of the second substrate or to the second surface of the stiffener. Additional electronic devices may be attached to the second surface of the second substrate.

Abstract translation: 描述了一种电和热增强的去离子球栅阵列（BGA）封装。 集成电路（IC）封装包括第一基板，第二基板和加强件。 第一基板的表面附接到加强件的第一表面。 第二基板的表面附接到加强件的第二表面。 IC芯片可以附接到第二基板的第二表面或者加强件的第二表面。 另外的电子设备可以附接到第二基板的第二表面。

公开(公告)号：US09570420B2

公开(公告)日：2017-02-14

申请号：US13248745

申请日：2011-09-29

Applicant: Jesus Alfonso Castaneda ,  Arya Reza Behzad ,  Ahmadreza Rofougaran ,  Sam Ziqun Zhao ,  Michael Boers

Inventor： Jesus Alfonso Castaneda ,  Arya Reza Behzad ,  Ahmadreza Rofougaran ,  Sam Ziqun Zhao ,  Michael Boers

IPC: H01L23/02 ,  H01L25/065 ,  H01P3/12 ,  H01L25/10 ,  G02B6/43 ,  G02B6/12 ,  H01L23/66 ,  H01L23/522 ,  H04L7/00 ,  H01P3/00

CPC classification number: H01L25/0657 ,  G02B6/12002 ,  G02B6/43 ,  H01L23/5222 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06572 ,  H01L2225/1005 ,  H01L2924/1461 ,  H01P3/00 ,  H01P3/12 ,  H01P3/121 ,  H04L7/0091 ,  H01L2924/00

Abstract: Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

Abstract translation: 公开了用于在集成电路内的集成电路和/或功能模块之间进行无线通信的方法和装置。 半导体器件制造操作使用预定的照相和/或化学处理步骤顺序在半导体衬底上形成一个或多个功能模块。 功能模块耦合到形成在半导体衬底上和/或连接到其上以形成集成电路的集成波导。 功能模块通过集成波导使用多址传输方案彼此通信以及其他集成电路。 一个或多个集成电路可以耦合到集成电路载体以形成多芯片模块。 多芯片模块可以耦合到半导体封装以形成封装的集成电路。

公开(公告)号：US09548251B2

公开(公告)日：2017-01-17

申请号：US13349045

申请日：2012-01-12

Applicant: Rezaur Rahman Khan ,  Sam Ziqun Zhao ,  Pieter Vorenkamp ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Xiangdong Chen

Inventor： Rezaur Rahman Khan ,  Sam Ziqun Zhao ,  Pieter Vorenkamp ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Xiangdong Chen

IPC: H01L23/48 ,  H01L23/13 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/13 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157

Abstract: A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

Abstract translation: 半导体封装可以包括衬底和具有空腔和多个通孔半导体通孔的半导体插入器。 半导体插入器位于衬底上。 插入式管芯设置在半导体插入器的空腔内。 导热粘合剂设置在空腔内并与内插器模具接触。 此外，顶部管芯位于半导体插入器上方。 在一个实现中，半导体插入器是硅插入器。 在另一个实施方式中，将半导体插入器倒装芯片安装到基板上，使得设置在空腔内的内插器芯片面向基板。 在又一实施方案中，半导体插入器中的空腔可以从半导体插入器的顶表面延伸到半导体插入器的底表面，并且热界面材料可以设置在内插器管芯和衬底之间。

公开(公告)号：US09008589B2

公开(公告)日：2015-04-14

申请号：US12877706

申请日：2010-09-08

Applicant: Ahmadreza (Reza) Rofougaran ,  Arya Reza Behzad ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

Inventor： Ahmadreza (Reza) Rofougaran ,  Arya Reza Behzad ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

IPC: H04B1/38 ,  G06F13/42 ,  H04B7/10 ,  G06F13/364 ,  H04W84/18

CPC classification number: G06F9/50 ,  H04B5/0037 ,  H04B7/10 ,  H04B7/26 ,  H04W4/80 ,  H04W84/18 ,  Y10T307/492

Abstract: Embodiments of the present invention are directed to a wireless-enabled component (WEC) for enabling a wireless bus for intra-chip and inter-chip communication. A WEC encompasses a functional block of an IC (such as, for example, a processing core of a processing unit), an entire IC (such as, for example, a processing unit), or a device that includes a plurality of ICs (such as, for example, a handheld device). According to embodiments, a WEC may be associated with one or more sub-blocks of an IC, a single IC, or a plurality of ICs.

Abstract translation: 本发明的实施例涉及一种能够使无线总线进行片内和芯片间通信的无线使能分量（WEC）。 WEC包括IC（例如处理单元的处理核心）的功能块，整个IC（例如，处理单元）或包括多个IC的设备（ 例如手持设备）。 根据实施例，WEC可以与IC，单个IC或多个IC的一个或多个子块相关联。

公开(公告)号：US09002673B2

公开(公告)日：2015-04-07

申请号：US13025657

申请日：2011-02-11

Applicant: Arya Reza Behzad ,  Ahmadreza Rofougaran ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

Inventor： Arya Reza Behzad ,  Ahmadreza Rofougaran ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

IPC: G01R31/14 ,  G01R31/28 ,  G01R31/302 ,  G01R31/311

CPC classification number: G01R31/2834 ,  G01R31/3025 ,  G01R31/311

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract translation: 公开了同时无线地测试形成在半导体晶片上的半导体元件的方法和装置。 半导体部件通过公共通信信道将各自的测试结果传送到无线自动测试设备。 多个接收天线在三维空间中观察多个方向的结果。 无线自动测试设备确定一个或多个半导体组件是否按预期运行，并且可选地，可以使用三维空间的属性来确定一个或多个半导体组件的位置。 无线测试设备还可以通过检测在独立测试操作之前，期间和/或之后由半导体晶片发射，传输和/或反射的红外能量来确定半导体组件的性能。