公开(公告)号：US20170213805A1

公开(公告)日：2017-07-27

申请号：US15483928

申请日：2017-04-10

Applicant: XINTEC INC.

Inventor： Chia-Lun SHEN ,  Yi-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/32 ,  H01L21/30604 ,  H01L21/48 ,  H01L21/78 ,  H01L24/05 ,  H01L24/09 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/12042 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.

公开(公告)号：US20170148694A1

公开(公告)日：2017-05-25

申请号：US15358098

申请日：2016-11-21

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Hsiao-Lan YEH ,  Chia-Sheng LIN ,  Yi-Ming CHANG ,  Po-Han LEE ,  Hui-Hsien WU ,  Jyun-Liang WU

IPC: H01L23/053 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L21/561 ,  G06K9/0004 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/16225

Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.

公开(公告)号：US20170040372A1

公开(公告)日：2017-02-09

申请号：US15226327

申请日：2016-08-02

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L27/14618 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer.

Abstract translation: 本发明提供了一种制造芯片级感测芯片封装的方法，包括以下步骤：提供具有彼此相对的第一顶表面和第一底表面的感测装置晶片，由此感测装置晶片包括多个芯片 区域，并且每个芯片区域包括感测装置和与第一顶表面附近的感测芯片相邻的多个导电焊盘; 提供具有彼此相对的第二顶表面和第二底表面的盖晶片，并且通过在其间夹住第一粘合剂层将盖晶片的第二表面粘合到感测装置晶片的第一顶表面; 提供临时载体基板，并且通过在其间夹着第二粘合剂层将临时载体基板结合到盖晶片的第二顶表面; 形成连接到感测装置晶片的第一底表面上的每个导电焊盘的布线层; 在所述布线层上提供第一保护层; 去除所述临时载体基板和所述第二粘合剂层; 在所述第二顶表面上形成第二保护层; 去除第一保护层; 划片芯片区域以产生多个单独的芯片级感测芯片封装; 并移除第二保护层。

公开(公告)号：US20160239699A1

公开(公告)日：2016-08-18

申请号：US15040280

申请日：2016-02-10

Applicant: XINTEC INC.

Inventor： Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: G06K9/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498 ,  H01L23/053

CPC classification number: G06K9/0002 ,  G06F3/03547 ,  G06F3/041 ,  G06F2203/04103 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/525 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2924/146 ,  H01L2924/15153 ,  H01L2924/15788 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/0311 ,  H05K2201/10151 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L21/78

Abstract: An embodiment of this invention provides a chip scale sensing chip package module, comprising a chip scale sensing chip package, having a sensing chip with a first top substrate and a first bottom substrate opposite to the first top substrate, wherein the sensing chip has a sensing device and a plurality of conductive pads adjacent to the first top substrate, and a plurality of conductive structures connected to the conductive pads by a re-distribution layer adjacent to the first bottom surface; a touch plate having a color layer, comprising a base and a spacer formed on the base, wherein the spacer has a cavity with a bottom wall exposing part of the surface of the base and a side wall surrounding the bottom wall; and a first adhesive layer sandwich between the sensing chip and the touch plate to join the first top surface of the sensing chip to the bottom wall of the cavity of the touch plate and surround the sensing chip by the side wall of the cavity; and a print circuit board placed under the chip scale sensing chip package by bonding the conductive structure of the chip scale sensing chip package to the print circuit board.

Abstract translation: 本发明的一个实施例提供了一种芯片级感测芯片封装模块，其包括芯片级感测芯片封装，其具有感测芯片，其具有第一顶部衬底和与第一顶部衬底相对的第一底部衬底，其中感测芯片具有感测 器件和与第一顶部衬底相邻的多个导电焊盘，以及多个导电结构，其通过与第一底表面相邻的再分配层连接到导电焊盘; 具有彩色层的触摸板，包括基部和形成在基底上的间隔件，其中所述间隔件具有腔体，所述空腔具有露出所述基部的所述表面的一部分的底壁和围绕所述底壁的侧壁; 并且第一粘合剂层夹在感测芯片和触摸板之间，以将感测芯片的第一顶表面接合到触摸板的腔的底壁，并且通过腔的侧壁围绕感测芯片; 以及通过将芯片尺度感测芯片封装的导电结构结合到印刷电路板上而放置在芯片尺度感测芯片封装下方的印刷电路板。

公开(公告)号：US20160039662A1

公开(公告)日：2016-02-11

申请号：US14747507

申请日：2015-06-23

Applicant: XINTEC INC.

Inventor： Chien-Min LIN ,  Yu-Ting HUANG ,  Chen-Ning FU ,  Yen-Shih HO

IPC: B81B7/00 ,  H01L21/48 ,  H01L23/498 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81C1/00182 ,  B81C1/00269 ,  B81C2201/0197 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.

Abstract translation: 芯片封装包括半导体芯片，插入件，聚合物粘合剂支撑层，再分布层和包装层。 半导体芯片具有传感器装置和与感测装置电连接的导电焊盘，并且插入器设置在半导体芯片上。 插入器具有沟槽和通孔，沟槽暴露感测装置的一部分，并且通孔暴露导电垫。 聚合物粘合剂支撑层插入在半导体芯片和插入件之间，并且再分配层设置在插入件上和通孔中以与导电焊盘电连接。 包装层覆盖插入件和再分配层，其中封装层具有露出沟槽的开口。

公开(公告)号：US20150340403A1

公开(公告)日：2015-11-26

申请号：US14703796

申请日：2015-05-04

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shu-Ming CHANG ,  Yung-Tai TSAI ,  Tsang-Yu LIU

IPC: H01L27/146 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01L27/14687 ,  H01L21/67092 ,  H01L21/6836 ,  H01L27/14685 ,  H01L31/18

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A second surface of the wafer is adhered to an ultraviolet tape on a frame, and the temporary bonding layer and the carrier are removed. A protection tape is adhered to the first surface of the wafer. An ultraviolet light is used to irradiate the ultraviolet tape. A dicing tape is adhered to the protection tape and the frame, and the ultraviolet tape is removed. A first cutter is used to dice the wafer from the second surface of the wafer, such that plural chips and plural gaps between the chips are formed. A second cutter with a width smaller than the width of the first cutter is used to cut the protection tape along the gaps.

Abstract translation: 半导体结构的制造方法包括以下步骤。 临时粘合层用于将载体粘附到晶片的第一表面。 将晶片的第二表面粘附到框架上的紫外线带上，并且移除临时粘合层和载体。 保护带粘附到晶片的第一表面。 使用紫外线照射紫外线带。 切割胶带粘附到保护带和框架上，并且除去紫外线带。 使用第一切割器从晶片的第二表面切割晶片，从而形成芯片之间的多个芯片和多个间隙。 使用宽度小于第一切割器的宽度的第二切割器沿着间隙切割保护带。

公开(公告)号：US20150279808A1

公开(公告)日：2015-10-01

申请号：US14673657

申请日：2015-03-30

Applicant: XINTEC INC.

Inventor： Chia-Lun SHEN ,  Yi-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/78

CPC classification number: H01L24/32 ,  H01L21/30604 ,  H01L21/48 ,  H01L21/78 ,  H01L24/05 ,  H01L24/09 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/12042 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.

Abstract translation: 提供一种形成芯片封装的方法。 该方法包括提供第一基板和第二基板。 第一衬底通过粘合剂层附着到第二衬底上。 形成第一开口以穿透第一基底和粘合剂层，并将第一基底和粘合剂层分离成部分。 还提供了通过该方法形成的芯片封装。

公开(公告)号：US20150228536A1

公开(公告)日：2015-08-13

申请号：US14618413

申请日：2015-02-10

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG ,  Shu-Ming CHANG ,  Tzu-Wen TSENG

IPC: H01L21/768 ,  H01L21/302 ,  H01L23/50

CPC classification number: H01L24/94 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/0657 ,  H01L2224/0224 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06165 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.

Abstract translation: 提供了包括半导体衬底的芯片封装。 凹部位于半导体衬底中并与半导体衬底的侧边相邻，其中半导体衬底具有从凹部的底部突出的至少一个间隔件。 导电层设置在半导体衬底上并延伸到凹槽中。

公开(公告)号：US20150162245A1

公开(公告)日：2015-06-11

申请号：US14596185

申请日：2015-01-13

Applicant: XINTEC INC.

Inventor： Bing-Siang CHEN ,  Chien-Hui CHEN ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L21/78 ,  H01L25/00

CPC classification number: H01L21/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在所述第一芯片上的第二芯片，其中所述第二芯片的侧表面是化学蚀刻表面; 以及设置在所述第一芯片和所述第二芯片之间的结合体，使得所述第一芯片和所述第二芯片彼此结合。

公开(公告)号：US20150123231A1

公开(公告)日：2015-05-07

申请号：US14534684

申请日：2014-11-06

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/0236 ,  H01L31/02

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了具有硅衬底和保护层的晶片结构。 保护层上的电焊盘通过硅衬底的凹入区露出。 在硅基板的侧壁上形成隔离层，该隔离层包围该凹陷区域以及该硅基板的远离该保护层的表面。 在隔离层和电焊盘上形成再分布层。 在再分布层上形成钝化层。 图案化钝化层以在其中形成第一开口。 在通过第一开口露出的再分布层上形成第一导电层。 导电结构布置在第一开口中，使得导电结构与第一导电层电接触。