公开(公告)号：US20170162511A1

公开(公告)日：2017-06-08

申请号：US15439145

申请日：2017-02-22

申请人： Applied Materials, Inc.

发明人： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Mei-yee SHEK

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L23/53238 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber, wherein the substrate comprises a copper layer having an exposed surface and a low-k dielectric layer having an exposed surface, forming a metal layer over the exposed surface of the copper layer, wherein the exposed surface of the low-k dielectric layer is free from the metal layer, and forming a metal-based dielectric layer over the metal layer and over at least part of the exposed low-k dielectric surface, wherein the metal-based dielectric layer comprises an aluminum compound.

公开(公告)号：US20170162502A1

公开(公告)日：2017-06-08

申请号：US15437128

申请日：2017-02-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chien Chi ,  Huang-Yi Huang ,  Szu-Ping Tung ,  Ching-Hua Hsieh

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/04 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76868 ,  H01L23/04 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present disclosure include a semiconductor device and methods of forming the same. A representative embodiment includes a method of forming a semiconductor device that includes a first conductive feature over a substrate, a dielectric layer over the conductive feature, and an opening through the dielectric layer to the first conductive feature. The method further includes selectively forming a first capping layer over the first conductive feature in the opening, and a second conductive feature on the first capping layer.

公开(公告)号：US20170162497A1

公开(公告)日：2017-06-08

申请号：US15370109

申请日：2016-12-06

申请人： Dyi-Chung HU

发明人： Dyi-Chung HU

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L21/7685 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2224/18

摘要： A filled metal via having an adhesive layer configured on bottom is disclosed. The adhesive layer enhances bonding force between the filled metal via and a bottom element. Further, stacked metal vias can be made to save spaces to enhance circuit density for an electronic system.

公开(公告)号：US09673132B2

公开(公告)日：2017-06-06

申请号：US14511006

申请日：2014-10-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiao Yun Lo ,  Yung-Chi Lin ,  Yang-Chih Hsueh ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L21/288 ,  H01L23/525

CPC分类号： H01L23/481 ,  H01L21/2885 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05005 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/1131 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/81805

摘要： An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

公开(公告)号：US09653353B2

公开(公告)日：2017-05-16

申请号：US13851885

申请日：2013-03-27

申请人： Novellus Systems, Inc.

发明人： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/285 ,  H01L27/105 ,  H01L27/108 ,  C23C16/04 ,  H01L21/321 ,  H01L21/3213

CPC分类号： H01L21/76879 ,  C23C16/045 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32136 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76898 ,  H01L27/1052 ,  H01L27/10891

摘要： Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

公开(公告)号：US20170125535A1

公开(公告)日：2017-05-04

申请号：US15272919

申请日：2016-09-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

发明人： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC分类号： H01L29/45 ,  H01L29/161 ,  H01L29/417 ,  H01L27/092 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/08 ,  H01L21/768

CPC分类号： H01L29/45 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

摘要： An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

公开(公告)号：US09640429B2

公开(公告)日：2017-05-02

申请号：US15053404

申请日：2016-02-25

申请人： Sumitomo Electric Device Innovations, Inc.

发明人： Masahiro Nishi

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L21/7685 ,  H01L21/28575 ,  H01L21/768 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76879 ,  H01L23/53219 ,  H01L29/2003 ,  H01L29/66462 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening pattern to the insulating film, the metal layer being exposed in the opening pattern; and forming a wiring layer in the opening pattern, a first portion being disposed between an edge of the wiring layer and an edge of the opening pattern, a width of the first portion being 1 μm or less, and the metal layer being exposed in the first portion.

公开(公告)号：US09633960B2

公开(公告)日：2017-04-25

申请号：US14755492

申请日：2015-06-30

申请人： SunASIC Technologies, Inc.

发明人： Chi-Chou Lin ,  Zheng-Ping He

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/78 ,  G06F3/044

CPC分类号： H01L24/06 ,  G06F3/044 ,  G06K9/00006 ,  G06K9/00013 ,  G06K9/0004 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L2223/5446 ,  H01L2224/03614 ,  H01L2224/05026 ,  H01L2224/06135 ,  H01L2224/0912

摘要： A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; at least two metal layers, formed above the substrate, each metal layer forming a specific circuit, wherein two adjacent metal layers are separated by an inter-metal dielectric layer; and a passivation layer, formed on a top side of the chip. By changing the I/O pad from the top of the chip to the peripheries, the extra thickness of the packaged chip caused by wire bonding in the prior arts can be reduced.

公开(公告)号：US09627321B2

公开(公告)日：2017-04-18

申请号：US14675613

申请日：2015-03-31

申请人： Intel Corporation

发明人： Boyan Boyanov ,  Kanwal Jit Singh

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528

CPC分类号： H01L23/53238 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

公开(公告)号：US09627320B2

公开(公告)日：2017-04-18

申请号：US13976008

申请日：2011-12-23

申请人： Rahul Panat ,  Bhanu Jaiswal

发明人： Rahul Panat ,  Bhanu Jaiswal

IPC分类号： H01L23/485 ,  H01L23/532 ,  B82Y30/00 ,  H01L21/02 ,  H01L29/06 ,  H01L23/498 ,  H01L21/768

CPC分类号： H01L23/53238 ,  B82Y30/00 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/76834 ,  H01L21/7685 ,  H01L23/49866 ,  H01L29/0673 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and devices including the formation of a layer of nanowires on wiring line traces are described. One device comprises a first dielectric layer and a plurality of traces on the first dielectric layer, the traces comprising Cu. The traces include a layer of ZnO nanowires positioned thereon. A second dielectric layer is positioned on the first dielectric layer and on the traces, wherein the second dielectric layer is in direct contact with the ZnO nanowires. Other embodiments are described and claimed.