公开(公告)号：US4194162A

公开(公告)日：1980-03-18

申请号：US889115

申请日：1978-03-22

申请人： Yutaka Uematsu ,  Yoichi Unno

发明人： Yutaka Uematsu ,  Yoichi Unno

IPC分类号： G02B6/30 ,  G02B5/18 ,  G02B6/293 ,  G02F1/35 ,  H01L31/14 ,  H01S5/00 ,  H01S5/042 ,  H01S5/187 ,  H01S3/19

CPC分类号： H01L31/143 ,  H01S5/187

摘要： A semiconductor device includes a semiconductor layer on one side of a semiconductor body to define a pn-junction therebetween, diffraction gratings formed at a distance from each other on the top of said semiconductor layer, and electrodes formed between the diffraction gratings on the top of said semiconductor and formed on the other side of the semiconductor body.

摘要翻译： 半导体器件包括在半导体本体的一侧上限定其间的pn结的半导体层，在所述半导体层顶部彼此间隔形成的衍射光栅和形成在所述半导体层顶部的衍射光栅之间的电极 所述半导体形成在半导体本体的另一侧。

公开(公告)号：US4176367A

公开(公告)日：1979-11-27

申请号：US885128

申请日：1978-03-10

申请人： Yutaka Uematsu

发明人： Yutaka Uematsu

IPC分类号： H04B10/00 ,  G02B6/42 ,  H01L31/04 ,  H01L31/12 ,  H01L33/00 ,  H01L33/14 ,  H01L33/20 ,  H01L33/30 ,  H01L33/38 ,  H04B10/43

CPC分类号： G02B6/4246 ,  H01L31/125 ,  H04B10/43

摘要： A semiconductor optical device includes a semiconductor body, a light emitting layer formed on the body to form a pn junction therebetween, a semiconductor layer formed on the light emitting layer and a diffusing region formed in the semiconductor layer to define a pn junction therebetween and electrically connected to the light emitting layer. Three electrodes are respectively provided on the semiconductor body, semiconductor layer and diffusing region, which are selectively operated.

摘要翻译： 半导体光学器件包括半导体本体，形成在主体上以在其间形成pn结的发光层，形成在发光层上的半导体层和形成在半导体层中的扩散区域，以在其间限定pn结，并且电 连接到发光层。 三个电极分别设置在半导体本体，半导体层和扩散区域上，这些电极被选择性地操作。

公开(公告)号：US20140103542A1

公开(公告)日：2014-04-17

申请号：US14109618

申请日：2013-12-17

申请人： Mitsuaki KATAGIRI ,  Ken Iwakura ,  Yutaka Uematsu

发明人： Mitsuaki KATAGIRI ,  Ken Iwakura ,  Yutaka Uematsu

IPC分类号： H01L23/498

CPC分类号： H01L23/498 ,  G11C5/06 ,  H01L23/525 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05013 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/49431 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.

摘要翻译： 半导体封装包括：半导体器件，包括多个信号焊盘和沿预定方向交替布置的多个辅助焊盘;以及封装板，包括多个信号键合指，多个第一电源电压键合指， 以及多个第二电源电压接合指。 信号焊盘通过第一线分别连接到信号键指。 第一电源电压键指和第二电源电压键合指通过第二线分别连接到辅助焊盘。 第一导线设置在连接到第一电源电压接合指的第二配线和连接到第二电源电压接合指的第二配线之间。

公开(公告)号：US20110239176A1

公开(公告)日：2011-09-29

申请号：US13155204

申请日：2011-06-07

申请人： Hideki OSAKA ,  Yutaka UEMATSU

发明人： Hideki OSAKA ,  Yutaka UEMATSU

IPC分类号： G06F17/50

CPC分类号： H05K3/0005 ,  H05K1/0231 ,  H05K2201/093

摘要： An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

摘要翻译： 仅通过执行电磁场分析一次形成正交阵列，并且通过使用电容器的安装位置和类型以及电容器数量作为参数来确定范围以进行电路分析次数少。 通过使用计算的电源阻抗的绝对值的结果作为指标来形成估计方程，并且通过使用估计方程来设置电容器以减少噪声。

公开(公告)号：US20110234249A1

公开(公告)日：2011-09-29

申请号：US13044717

申请日：2011-03-10

申请人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

发明人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

IPC分类号： G01R31/00

CPC分类号： G01R31/2889

摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

摘要翻译： 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

公开(公告)号：US07939907B2

公开(公告)日：2011-05-10

申请号：US11755045

申请日：2007-05-30

申请人： Hideki Osaka ,  Yutaka Uematsu ,  Eiichi Suzuki

发明人： Hideki Osaka ,  Yutaka Uematsu ,  Eiichi Suzuki

IPC分类号： H01L29/00 ,  H01L23/52

CPC分类号： H05K1/0236 ,  H01L23/66 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/09972 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： High density mounting and power source sharing are achieved by a digital semiconductor element and an analog semiconductor element provided in a common semiconductor device. A power layer for analog operation is connected to one end of an EBG (Electromagnetic Band Gap) layer, a power layer for digital operation is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog operation and the EBG layer from each other is disposed between the power layer for analog operation and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of the power source to an analog chip.

摘要翻译： 通过设置在公共半导体器件中的数字半导体元件和模拟半导体元件来实现高密度安装和电源共享。 用于模拟操作的功率层连接到EBG（电磁带隙）层的一端，用于数字操作的功率层连接到EBG层的另一端，各个元件的接地端子连接到公共地 层和用于模拟操作的功率层和EBG层之间分离的接地层设置在用于模拟操作的功率层和EBG层之间。 从而，实现了高密度安装，同时减少了电源对模拟芯片的干扰。

公开(公告)号：US07768867B2

公开(公告)日：2010-08-03

申请号：US11761470

申请日：2007-06-12

申请人： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

发明人： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

IPC分类号： G11C8/00

CPC分类号： G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

摘要翻译： 叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。 堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。 作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。 数据选通信号和反相数据选通信号相互配合。 用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘 存储芯片12。

公开(公告)号：US20100013528A1

公开(公告)日：2010-01-21

申请号：US12504319

申请日：2009-07-16

申请人： Yutaka Uematsu ,  Tatsuya Saito ,  Yoji Nishio ,  Yukitoshi Hirose

发明人： Yutaka Uematsu ,  Tatsuya Saito ,  Yoji Nishio ,  Yukitoshi Hirose

IPC分类号： H03L5/00

CPC分类号： G11C11/406 ,  G11C11/40618 ,  G11C11/4074 ,  G11C2211/4067

摘要： A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.

摘要翻译： 半导体器件或信息处理系统包括多个电路单元，以及控制单元，用于在预定时间段内控制由各个电路单元执行的大电流操作的开始定时，其中大电流操作涉及相对大的 与其他操作相比，在电源系统中流动的电流。 控制单元控制从一个电路单元到另一个电路单元的大电流操作的开始定时，使得当电路单元执行时，从电源系统流过的电流的波形被成形为正弦波的半周期的波形 在预定时段内的大电流操作。

公开(公告)号：US20080290495A1

公开(公告)日：2008-11-27

申请号：US12068606

申请日：2008-02-08

申请人： Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

发明人： Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

IPC分类号： H01L23/528

CPC分类号： H05K1/0231 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/09 ,  H05K1/111 ,  H05K1/167 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

摘要： As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.

摘要翻译： 作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。 通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持 阻抗低在低频。

公开(公告)号：US20080266031A1

公开(公告)日：2008-10-30

申请号：US12060941

申请日：2008-04-02

申请人： Yutaka UEMATSU ,  Hideki Osaka ,  Yoji Nishio ,  Eiichi Suzuki

发明人： Yutaka UEMATSU ,  Hideki Osaka ,  Yoji Nishio ,  Eiichi Suzuki

IPC分类号： H01P1/00

CPC分类号： H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/111 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10734 ,  H01L2924/00

摘要： A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 μm therebetween.

摘要翻译： 提供了能够实现半导体器件的安装密度和噪声降低的改进的技术。 安装在印刷电路板上的LSI包括接地BGA球和电源BGA球，以从印刷线路板获得电源，并且接地BGA球和电源BGA球彼此靠近地布置。 去耦电容器安装在印刷电路板上，并具有第一端子和第二端子。 接地BGA球和第一端子通过第一金属电极板连接，电力BGA球和第二端子通过第二金属电极板连接。 第一金属电极板和第二金属电极板在其间插入厚度等于或小于1μm的电介质膜。