公开(公告)号：US20120119387A1

公开(公告)日：2012-05-17

申请号：US13291740

申请日：2011-11-08

申请人： Mitsuaki KATAGIRI ,  Ken Iwakura ,  Yutaka Uematsu

发明人： Mitsuaki KATAGIRI ,  Ken Iwakura ,  Yutaka Uematsu

IPC分类号： H01L23/50 ,  H01L23/522

CPC分类号： H01L23/498 ,  G11C5/06 ,  H01L23/525 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05013 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/49431 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.

摘要翻译： 半导体封装包括：半导体器件，包括多个信号焊盘和沿预定方向交替布置的多个辅助焊盘;以及封装板，包括多个信号键合指，多个第一电源电压键合指， 以及多个第二电源电压接合指。 信号焊盘通过第一线分别连接到信号键指。 第一电源电压键指和第二电源电压键合指通过第二线分别连接到辅助焊盘。 第一导线设置在连接到第一电源电压接合指的第二配线和连接到第二电源电压接合指的第二配线之间。

公开(公告)号：US20120200159A1

公开(公告)日：2012-08-09

申请号：US13366717

申请日：2012-02-06

申请人： Mitsuaki KATAGIRI ,  Ken Iwakura ,  Yutaka Uematsu

发明人： Mitsuaki KATAGIRI ,  Ken Iwakura ,  Yutaka Uematsu

IPC分类号： H02J4/00

CPC分类号： H03K19/00361 ,  G11C7/02 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096 ,  Y10T307/50

摘要： A semiconductor device includes: first and second power supply wirings VDDQ and VSSQ, respectively; an output circuit 12 arranged between VDDQ and VSSQ; and a noise cancellation circuit 13 arranged between VDDQ and VSSQ. The noise cancellation circuit 13 produces a damped oscillation for the SSN oscillation noise that is generated when a logic level outputted to an output node of the output circuit is switched and that exponentially damps and oscillates at a predetermined period. The damped oscillation produced by the noise cancellation circuit 13 is delayed by half a period of the SSN oscillation noise and has a direction opposite to that of the SSN oscillation noise and hence the damped oscillation and the SSN oscillation noise counteract each other.

摘要翻译： 半导体器件分别包括：第一和第二电源配线VDDQ和VSSQ; 布置在VDDQ和VSSQ之间的输出电路12; 以及布置在VDDQ和VSSQ之间的噪声消除电路13。 噪声消除电路13产生用于当输出到输出电路的输出节点的逻辑电平被切换并且以预定周期指数衰减和振荡时产生的SSN振荡噪声的阻尼振荡。 由噪声消除电路13产生的阻尼振荡被延迟SSN振荡噪声的一半周期，并且具有与SSN振荡噪声相反的方向，因此阻尼振荡和SSN振荡噪声相互抵消。

公开(公告)号：US20140103542A1

公开(公告)日：2014-04-17

申请号：US14109618

申请日：2013-12-17

申请人： Mitsuaki KATAGIRI ,  Ken Iwakura ,  Yutaka Uematsu

发明人： Mitsuaki KATAGIRI ,  Ken Iwakura ,  Yutaka Uematsu

IPC分类号： H01L23/498

CPC分类号： H01L23/498 ,  G11C5/06 ,  H01L23/525 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05013 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/49431 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.

摘要翻译： 半导体封装包括：半导体器件，包括多个信号焊盘和沿预定方向交替布置的多个辅助焊盘;以及封装板，包括多个信号键合指，多个第一电源电压键合指， 以及多个第二电源电压接合指。 信号焊盘通过第一线分别连接到信号键指。 第一电源电压键指和第二电源电压键合指通过第二线分别连接到辅助焊盘。 第一导线设置在连接到第一电源电压接合指的第二配线和连接到第二电源电压接合指的第二配线之间。

公开(公告)号：US20110234249A1

公开(公告)日：2011-09-29

申请号：US13044717

申请日：2011-03-10

申请人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

发明人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

IPC分类号： G01R31/00

CPC分类号： G01R31/2889

摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

摘要翻译： 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

公开(公告)号：US20100193933A1

公开(公告)日：2010-08-05

申请号：US12687311

申请日：2010-01-14

申请人： Yu HASEGAWA ,  Mitsuaki KATAGIRI ,  Satoshi ISA ,  Ken IWAKURA ,  Dai SASAKI

发明人： Yu HASEGAWA ,  Mitsuaki KATAGIRI ,  Satoshi ISA ,  Ken IWAKURA ,  Dai SASAKI

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85007 ,  H01L2224/85051 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48132 ,  H01L2924/00012 ,  H01L2924/20757 ,  H01L2924/2075 ,  H01L2924/20754 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.

摘要翻译： 在本发明的半导体器件中，第二半导体芯片堆叠在其中心区域具有多个接合焊盘的第一半导体芯片上，其间插入有接合层。 通过穿过第一和第二半导体芯片之间的空间，分别连接到第一半导体芯片的多个接合焊盘的多条引线在第一半导体芯片的外围边缘被引出到外部。 在第一半导体芯片上的区域中设置用于保持多条电线的至少一个子集的保持构件，该区域包括通过使用不同于接合层的材料，在接合焊盘与第一半导体芯片的周边边缘之间的中间点 使得电线的子集通常位于第一半导体芯片和第二半导体芯片之间的间隔的中心。

公开(公告)号：US20130114223A1

公开(公告)日：2013-05-09

申请号：US13463317

申请日：2012-05-03

申请人： Satoshi ITAYA ,  Satoshi ISA ,  Mitsuaki KATAGIRI ,  Dai SASAKI

发明人： Satoshi ITAYA ,  Satoshi ISA ,  Mitsuaki KATAGIRI ,  Dai SASAKI

IPC分类号： H05K1/18

CPC分类号： H05K1/181 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.

摘要翻译： 在数据输出电路中，半导体器件减少了用于提供具有电源电压或接地电压以及数据信号传输加速的数据输出电路的电路的布线的阻抗。 附加的基板2a，2b位于半导体芯片1的上表面上。形成在各个附加基板2a，2b上的用于电源10d的第一附加布线层和用于接地的第一附加布线层10形成半导体芯片1上规定的导电区域。 源极配线40C1d或第一接地配线40C1通过附加配线层10d和10s相互连接。 与DQ系统信号线40CDQ相同的方向延伸的第二电源配线40C2d和第二接地配线40C2s形成反馈电流路径。 第二电源配线40C2d和第二接地配线40C2s配置在与DQ系统信号配线40CDQ相邻的位置。

公开(公告)号：US20090184409A1

公开(公告)日：2009-07-23

申请号：US12357895

申请日：2009-01-22

申请人： Mitsuaki KATAGIRI ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

发明人： Mitsuaki KATAGIRI ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

IPC分类号： H01L23/02 ,  H01L25/10 ,  H01L23/48 ,  H01L23/485

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00

摘要： In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

摘要翻译： 在层叠型半导体器件中，堆叠第一半导体器件和至少一个第二半导体器件。 第一半导体器件包括布线板和安装在布线板上的第一半导体芯片。 第二半导体器件包括布线板和安装在布线板上的第二半导体芯片。 每个第二半导体器件的第二半导体芯片的厚度比第一半导体芯片的厚度厚。

公开(公告)号：US20080072194A1

公开(公告)日：2008-03-20

申请号：US11854591

申请日：2007-09-13

申请人： Mitsuaki KATAGIRI ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

发明人： Mitsuaki KATAGIRI ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

摘要翻译： 公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。 第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。 第二半导体芯片包括耦合到输入焊盘的输出焊盘。 调整对象被连接到第一和第二半导体芯片。 主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。 考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型 芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。 将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

公开(公告)号：US20120302007A1

公开(公告)日：2012-11-29

申请号：US13538654

申请日：2012-06-29

申请人： Mitsuaki KATAGIRI ,  Hisashi TANIE ,  Jun KAYAMORI ,  Dai SASAKI ,  Hiroshi MORIYA

发明人： Mitsuaki KATAGIRI ,  Hisashi TANIE ,  Jun KAYAMORI ,  Dai SASAKI ,  Hiroshi MORIYA

IPC分类号： H01L21/60

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00

摘要： In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

摘要翻译： 在层叠型半导体器件中，堆叠第一半导体器件和至少一个第二半导体器件。 第一半导体器件包括布线板和安装在布线板上的第一半导体芯片。 第二半导体器件包括布线板和安装在布线板上的第二半导体芯片。 每个第二半导体器件的第二半导体芯片的厚度比第一半导体芯片的厚度厚。

公开(公告)号：US20120061826A1

公开(公告)日：2012-03-15

申请号：US13192065

申请日：2011-07-27

申请人： Yu HASEGAWA ,  Mitsuaki KATAGIRI

发明人： Yu HASEGAWA ,  Mitsuaki KATAGIRI

IPC分类号： H01L23/498 ,  H01L23/522

CPC分类号： H01L23/49811 ,  H01L23/13 ,  H01L23/538 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/49426 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

摘要： A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

摘要翻译： 一种器件包括衬底，半导体芯片，第一和第二焊盘以及第一布线层。 基板包括第一和第二表面。 半导体芯片包括第三和第四表面。 第三表面朝向第一表面。 第一和第二焊盘设置在第三表面上。 第一和第二焊盘彼此连接。 第一布线层设置在基板的第二表面上。 第一布线层连接到第一焊盘。