公开(公告)号：US07855443B2

公开(公告)日：2010-12-21

申请号：US11732853

申请日：2007-04-04

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

摘要翻译： 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。

公开(公告)号：US07666716B2

公开(公告)日：2010-02-23

申请号：US12367723

申请日：2009-02-09

申请人： Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module to form an encapsulant encapsulating the semiconductor chip, exposing the electrical connecting points from the encapsulant; forming a patterned circuit layer on the encapsulant, electrically connecting the patterned circuit layer to the electrical connecting points, cutting and separating the chip carriers to form a plurality of semiconductor packages each having a circuit layer formed on the encapsulant such that the circuit layer provides extra electrical connecting points and thereby enhances electrical performance of electrical products. During a package stacking process, no package is limited by the design of another package below.

摘要翻译： 本发明提供半导体封装及其制造方法。 该方法包括以下步骤：提供具有多个芯片载体的芯片载体模块，在芯片载体上布置多个电连接点，在芯片载体模块上执行芯片安装和模制以形成封装半导体芯片的密封剂， 将电连接点暴露于密封剂; 在所述密封剂上形成图案化电路层，将所述图案化电路层电连接到所述电连接点，切割和分离所述芯片载体以形成多个半导体封装，每个半导体封装具有形成在所述密封剂上的电路层，使得所述电路层提供额外的 电连接点，从而提高电气产品的电气性能。 在包装堆垛过程中，没有包装受下面另一包装的设计限制。

公开(公告)号：US20090146285A1

公开(公告)日：2009-06-11

申请号：US12367723

申请日：2009-02-09

申请人： Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module to form an encapsulant encapsulating the semiconductor chip, exposing the electrical connecting points from the encapsulant; forming a patterned circuit layer on the encapsulant, electrically connecting the patterned circuit layer to the electrical connecting points, cutting and separating the chip carriers to form a plurality of semiconductor packages each having a circuit layer formed on the encapsulant such that the circuit layer provides extra electrical connecting points and thereby enhances electrical performance of electrical products. During a package stacking process, no package is limited by the design of another package below.

摘要翻译： 本发明提供半导体封装及其制造方法。 该方法包括以下步骤：提供具有多个芯片载体的芯片载体模块，在芯片载体上布置多个电连接点，在芯片载体模块上执行芯片安装和模制以形成封装半导体芯片的密封剂， 将电连接点暴露于密封剂; 在所述密封剂上形成图案化电路层，将所述图案化电路层电连接到所述电连接点，切割和分离所述芯片载体以形成多个半导体封装，每个半导体封装具有形成在所述密封剂上的电路层，使得所述电路层提供额外的 电连接点，从而提高电气产品的电气性能。 在包装堆垛过程中，没有包装受下面另一包装的设计限制。

公开(公告)号：US06498054B1

公开(公告)日：2002-12-24

申请号：US09585964

申请日：2000-06-02

申请人： Shih-Kuang Chiu ,  Ying-Chou Tsai ,  Han-Ping Pu

发明人： Shih-Kuang Chiu ,  Ying-Chou Tsai ,  Han-Ping Pu

IPC分类号： H01L2144

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/15151 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： A flip-chip underfill method is proposed for the purpose of underfilling a gap formed beneath a semiconductor chip mounted in a flip-chip manner over an underlying surface. The flip-chip underfill method comprises the following procedural steps of: preparing a dispensing needle having an outlet; then, moving the dispensing needle in such a manner as to position the outlet thereof at a corner point between the upper surface and the sidewall of the semiconductor chip; and finally injecting resin at the targeted corner point, which allows the injected resin from the outlet of the dispensing needle to flow down along the sidewall of the semiconductor chip to the edge of the lower surface of the semiconductor chip and subsequently fill into the gap through capillary action. This flip-chip underfill method is more advantageous to use than the prior art since it allows the dispensing needle to be unobstructed by any gold wires or passive components mounted beside the chip and also allows the injected resin to be substantially confined to the targeted area beneath the chip without being wasted.

摘要翻译： 提出了一种倒装底层填充方法，其目的在于在底层表面上以倒装芯片的方式填充形成在半导体芯片下面的间隙。 倒装底层填充方法包括以下步骤：准备具有出口的分配针; 然后，以将出口定位在半导体芯片的上表面和侧壁之间的角点处的方式移动分配针; 并且最终在目标角点注入树脂，这允许来自分配针的出口的注入的树脂沿着半导体芯片的侧壁向下流到半导体芯片的下表面的边缘，随后填充到间隙中 毛细作用。 这种倒装底层填充方法比现有技术更有利于使用，因为其允许分配针由安装在芯片旁边的任何金线或无源元件不受阻碍，并且还允许注入的树脂基本上限制在下面的目标区域 芯片不被浪费。

公开(公告)号：US06291264B1

公开(公告)日：2001-09-18

申请号：US09629072

申请日：2000-07-31

申请人： Wei-Sen Tang ,  Han-Ping Pu

发明人： Wei-Sen Tang ,  Han-Ping Pu

IPC分类号： H01L2144

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L24/28 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A flip-chip package technology is proposed for use to fabricate a dual-chip integrated circuit package that includes two semiconductor chips in a single package unit, which is characterized in the forming of a flash-barrier structure that can help prevent the underfill material used in flip-chip underfill process from flashing to other unintended areas. The flash-barrier structure can be either a protruded dam structure over the underlying semiconductor chip, or a groove in a coating layer formed over the underlying semiconductor chip. During flip-chip underfill process, the flash-barrier structure can confine the underfill material within the intended area and prevent the underfill material from flowing to other unintended areas such as nearby bonding pads, so that the finished package product can be assured in quality and reliability.

摘要翻译： 提出了一种倒装芯片封装技术，用于制造双芯片集成电路封装，其包括在单个封装单元中的两个半导体芯片，其特征在于形成闪光屏障结构，其可以帮助防止使用的底部填充材料 在从闪烁到其他非预期区域的倒装芯片底部填充过程中。 闪光屏障结构可以是下面的半导体芯片上的突出的坝结构，也可以是形成在下面的半导体芯片上的涂层中的凹槽。 在倒装芯片底部填充过程中，闪光屏障结构可以将底部填充材料限制在预期区域内，并防止底部填充材料流到其他非预期区域（例如附近的焊盘），从而可以确保成品包装产品的质量和 可靠性。

公开(公告)号：US06281578B1

公开(公告)日：2001-08-28

申请号：US09638989

申请日：2000-08-15

申请人： Randy H. Y. Lo ,  Chi-Chuan Wu ,  Han-Ping Pu ,  Eric Ko

发明人： Randy H. Y. Lo ,  Chi-Chuan Wu ,  Han-Ping Pu ,  Eric Ko

IPC分类号： H01L2334

CPC分类号： H01L23/49531 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A multi-chip module (MCM) integrated circuit package structure is proposed, which can be used to pack a plurality of semiconductor chips of different functions while nonetheless allowing the overall package size to be as small as some existing types of integrated circuit packages, such as the SO (Small Outline) and QFP (Quad Flat Package) types, so that it can be manufactured using the existing fabrication equipment. The proposed MCM integrated circuit package structure is characterized in the use of a substrate having a centrally-located opening, and at least one semiconductor chip is mounted on the front surface of the substrate and a semiconductor chip of a central-pad type having a plurality of centrally-located bonding pads is mounted on the back surface of the substrate with the centrally-located bonding pads being exposed through the opening. This arrangement allows the overall package size to be made very compact and also allows the wiring to the central-pad type semiconductor chip to be shortened.

摘要翻译： 提出了一种多芯片模块（MCM）集成电路封装结构，可用于封装多个不同功能的半导体芯片，同时允许整体封装尺寸与现有类型的集成电路封装一样小，如 作为SO（小外形）和QFP（四方扁平封装）类型，因此可以使用现有的制造设备制造。 所提出的MCM集成电路封装结构的特征在于使用具有居中定位的开口的衬底，并且至少一个半导体芯片安装在衬底的前表面上，以及具有多个中心焊盘的半导体芯片 中心定位的焊盘安装在基板的背面，中心位置的焊盘通过开口露出。 这种布置使得整体封装尺寸变得非常紧凑，并且还允许缩短到中心焊盘型半导体芯片的布线。

公开(公告)号：US09041223B2

公开(公告)日：2015-05-26

申请号：US13610050

申请日：2012-09-11

申请人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

发明人： Yuh Chern Shieh ,  Han-Ping Pu ,  Yu-Feng Chen ,  Tin-Hao Kuo

IPC分类号： H01L23/40 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/44 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L24/14 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1405 ,  H01L2224/14131 ,  H01L2224/145 ,  H01L2224/16104 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/05552

摘要： A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

摘要翻译： 描述了跟踪（BOT）结构。 BOT结构包括在第一工件的表面上具有金属迹线的第一工件，其中金属迹线具有第一轴线。 BOT结构还包括具有细长金属凸块的第二工件，其中细长金属凸块具有第二轴线，其中第二轴线与第一轴线成非零角度。 BOT结构还包括金属凸块，其中金属凸块电连接金属迹线和细长金属凸块。 还描述了具有BOT结构的封装和形成BOT结构的方法。

公开(公告)号：US08400178B2

公开(公告)日：2013-03-19

申请号：US12431927

申请日：2009-04-29

申请人： Han-Ping Pu ,  Mill-Jer Wang

发明人： Han-Ping Pu ,  Mill-Jer Wang

IPC分类号： G01R31/02

CPC分类号： H01L23/345 ,  G01R31/2856 ,  G01R31/2875 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a semiconductor device, the device includes a substrate, a front-end structure formed in the substrate, a back-end structure formed on the front-end structure, a heater embedded in the back-end structure and operable to generate heat, and a sensor embedded in the back-end structure and operable to sense a temperature of the semiconductor device.

摘要翻译： 本公开提供一种半导体器件，该器件包括衬底，形成在衬底中的前端结构，形成在前端结构上的后端结构，嵌入在后端结构中的加热器，可操作以产生 热和嵌入在后端结构中的传感器，并且可操作以感测半导体器件的温度。

公开(公告)号：US20120306067A1

公开(公告)日：2012-12-06

申请号：US13151720

申请日：2011-06-02

申请人： Pei-Haw Tsao ,  Kuo-Chin Chang ,  Han-Ping Pu

发明人： Pei-Haw Tsao ,  Kuo-Chin Chang ,  Han-Ping Pu

IPC分类号： H01L23/488 ,  H01L23/36 ,  H01L21/50

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/92 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/19 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/00

摘要： According to an embodiment, an integrated circuit package comprises a chip, a thermal component, and a molding compound. The chip comprises an active surface and a backside surface opposite the active surface. The thermal component is physically coupled to the backside surface of the chip. The molding compound encapsulates the chip, and an exposed surface of the thermal component is exposed through the molding compound. Another embodiment is a method to form an integrated circuit package.

摘要翻译： 根据实施例，集成电路封装包括芯片，热部件和模制化合物。 芯片包括有源表面和与有源表面相对的背面。 热分量物理耦合到芯片的背面。 模塑料包封芯片，并且通过模塑料露出热组分的暴露表面。 另一实施例是形成集成电路封装的方法。

公开(公告)号：US20110070697A1

公开(公告)日：2011-03-24

申请号：US12955256

申请日：2010-11-29

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/48

CPC分类号： H01L25/105 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

摘要翻译： 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置相对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。