公开(公告)号：US20190140158A1

公开(公告)日：2019-05-09

申请号：US14229820

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Shawna M. Liff

IPC: H01L41/053 ,  H01L41/047 ,  H01L41/23

Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.

公开(公告)号：US10116504B2

公开(公告)日：2018-10-30

申请号：US15283129

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Sasha N. Oster ,  Feras Eid ,  Georgios C. Dogiamis ,  Thomas L. Sounart ,  Johanna M. Swan

IPC: H01L41/047 ,  H01L41/09 ,  H04L12/24 ,  H01H57/00 ,  H01L41/187 ,  A61B5/0205 ,  A61B5/00 ,  A61B5/024 ,  A61B5/021 ,  A61B5/08 ,  A61B5/145

Abstract: Embodiments of the invention include a physiological sensor system. According to an embodiment the sensor system may include a package substrate, a plurality of sensors formed on the substrate, a second electrical component, and an encryption bank formed along a data transmission path between the plurality of sensors and the second electrical component. In an embodiment the encryption bank may include a plurality of portions that each have one or more switches integrated into the package substrate. In an embodiment each sensor transmits data to the second electrical component along different portions of the encryption bank. In some embodiments, the switches may be piezoelectrically actuated. In other embodiments the switches may be actuated by thermal expansion. Additional embodiments may include tri- or bi-stable mechanical switches.

公开(公告)号：US10032052B2

公开(公告)日：2018-07-24

申请号：US15586820

申请日：2017-05-04

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Telesphor Kamgaing ,  Feras Eid ,  Vijay K. Nair ,  Georgios C. Dogiamis ,  Johanna M. Swan ,  Valluri R. Rao

IPC: G06K19/06 ,  G06K7/10 ,  H03H9/30 ,  G06K19/067

Abstract: Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of conductive layers form the organic substrate. The delay line circuitry includes a piezoelectric transducer to receive a guided electromagnetic wave signal and to generate an acoustic wave signal to be transmitted with an acoustic transmission medium. An acoustic reflector is communicatively coupled to the acoustic transmission medium. The acoustic reflector receives a plurality of acoustic wave signals from the acoustic transmission medium and reflects acoustic wave signals to the piezoelectric transducer using the acoustic transmission medium. The transducer converts the reflected acoustic signals into electromagnetic waves which are then transmitted back through the antenna and decoded by the reader.

公开(公告)号：US09992859B2

公开(公告)日：2018-06-05

申请号：US14866693

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew Manusharow ,  Krishna Bharath ,  Zhichao Zhang ,  Yidnekachew S. Mekonnen ,  Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Javier Soto

IPC: H05K1/02 ,  H01P3/02 ,  H01P3/08

CPC classification number: H05K1/0245 ,  H01P3/02 ,  H01P3/026 ,  H01P3/08 ,  H01P3/085 ,  H01P3/088

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US09893438B1

公开(公告)日：2018-02-13

申请号：US15281814

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Adel A. Elsherbini ,  Feras Eid ,  Aleksandar Aleksov ,  Amit Sudhir Baxi ,  Johanna M. Swan ,  Vincent S. Mageshkumar

IPC: A61B17/00 ,  H01R4/58 ,  H01R43/26 ,  H01R13/03 ,  A44B17/00 ,  A44B19/24

CPC classification number: H01R4/58 ,  A44B17/0041 ,  A44B19/24 ,  H01R13/03 ,  H01R43/26

Abstract: A system can include a first portion of a fabric fastener, a second portion of the fabric fastener, wherein the first portion and the second portion are configured to mechanically connect with each other and to resist separation from each other once connected, and wherein the first and second portions include a plurality of corresponding electrical contacts configured to form a plurality of individual electrical connections when the first portion is mechanically connected with the second portion.

公开(公告)号：US09865521B2

公开(公告)日：2018-01-09

申请号：US15410625

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Chandra M. Jha ,  Feras Eid ,  Johanna M. Swan ,  Ashish Gupta

IPC: H01L23/34 ,  H01L23/373 ,  H01L23/00

CPC classification number: H01L23/3733 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/433 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/1133 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11826 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13078 ,  H01L2224/13147 ,  H01L2224/13193 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/271 ,  H01L2224/27436 ,  H01L2224/2745 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29347 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2924/3511 ,  Y10T428/249921 ,  Y10T428/26 ,  H01L2224/27 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00014

Abstract: A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

公开(公告)号：US09820384B2

公开(公告)日：2017-11-14

申请号：US14102676

申请日：2013-12-11

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravi V. Mahajan ,  James C. Matayabas, Jr. ,  Johanna Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H05K13/04 ,  H01L23/00 ,  H05K1/03 ,  G06F1/16 ,  H01L21/56

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

公开(公告)号：US09791470B2

公开(公告)日：2017-10-17

申请号：US14141759

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Feras Eid ,  Sasha N. Oster ,  Kyu Oh Lee ,  Sarah Haney

IPC: H01L27/22 ,  G01P1/04 ,  G01P15/097 ,  B81C1/00 ,  B81B3/00 ,  B81B7/00

CPC classification number: G01P1/04 ,  B81B3/0027 ,  B81B7/007 ,  B81B7/008 ,  B81B2201/025 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/094 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00547 ,  B81C2201/056 ,  B81C2203/0172 ,  B81C2203/0714 ,  B81C2203/0792 ,  G01P15/097 ,  H01L27/22 ,  Y10T29/49075

Abstract: Magnet placement is described for integrated circuit packages. In one example, a terminal is applied to a magnet. The magnet is then placed on a top layer of a substrate with solder between the terminal and the top layer, and the solder is reflowed to attach the magnet to the substrate.

公开(公告)号：US20170092561A1

公开(公告)日：2017-03-30

申请号：US14863580

申请日：2015-09-24

Applicant: INTEL CORPORATION

Inventor： Feras Eid ,  Arnab Choudhury

IPC: H01L23/427 ,  H01L25/065 ,  H01L21/48 ,  H01L23/373

CPC classification number: H01L23/427 ,  H01L21/4878 ,  H01L21/4882 ,  H01L23/3675 ,  H01L23/373 ,  H01L23/433 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/73253

Abstract: A thermal management solution may be provided for a microelectronic system, wherein a jumping drops vapor chamber is utilized between at least one microelectronic device and an integrated heat spreader. The microelectronic system may comprise a microelectronic device attached by an active surface thereof to a microelectronic substrate. The integrated heat spreader, having a first surface and an opposing second surface, is also attached to the microelectronic substrate with a jumping drops vapor chamber disposed between a back surface of the microelectronic device and the integrated heat spreader second surface. The jumping drops vapor chamber may comprise a vapor space defined by a hydrophilic evaporation surface on the microelectronic device back surface, a hydrophobic condensation surface on the integrated heat spreader second surface, and at least one sidewall extending between the hydrophilic evaporation surface and the hydrophobic condensation surface with a working fluid disposed within the vapor space.

公开(公告)号：US09345184B2

公开(公告)日：2016-05-17

申请号：US14126271

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Sarah Haney ,  Weng Hong Teh ,  Feras Eid

IPC: H05K9/00 ,  H01L23/552 ,  H01L23/00 ,  B32B37/24 ,  B32B38/10 ,  B81B7/00 ,  B81B7/02 ,  G06F1/18 ,  H05K1/11 ,  H01L21/56

CPC classification number: H05K9/0052 ,  B32B37/24 ,  B32B38/10 ,  B32B2037/243 ,  B32B2457/00 ,  B81B7/0029 ,  B81B7/0032 ,  B81B7/02 ,  B81C1/0023 ,  G06F1/182 ,  H01L21/568 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1461 ,  H05K1/115 ,  Y10T156/10 ,  H01L2924/00

Abstract: Magnetic field shielding material with high relative permeability incorporated into a build-up package, for example to restrict a field of a magnet integrated with the build-up to a target device configured to operate in the field. In embodiments, a first device is physically coupled to the build-up. In embodiments, a magnetic field shielding material is disposed in contact with the build-up and in proximity to the first device to restrict a magnetic field either to a region occupied by the first device or to a region exclusive of the first device. A field shielding material may be disposed within build-up near a permanent magnet also within the build-up to reduce exposure of another device, such as an IC, to the magnetic field without reducing MEMS device exposure.

Abstract translation: 具有高的相对磁导率的磁场屏蔽材料被并入到积聚封装中，例如将与积聚物集成的磁体的场限制到被配置为在现场操作的目标装置。 在实施例中，第一设备物理地耦合到建立。 在实施例中，磁场屏蔽材料设置成与积层接触并且靠近第一装置，以将磁场限制到由第一装置占据的区域或不包括第一装置的区域。 场屏蔽材料也可以在堆积物内的永磁体附近的堆积内设置，以减少诸如IC之类的其它器件（例如IC）的暴露，而不会降低MEMS器件的暴露。