公开(公告)号：US09947618B2

公开(公告)日：2018-04-17

申请号：US15619160

申请日：2017-06-09

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/04 ,  H01L23/52 ,  H01L21/44 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US20170374738A1

公开(公告)日：2017-12-28

申请号：US15682049

申请日：2017-08-21

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

公开(公告)号：US09741696B2

公开(公告)日：2017-08-22

申请号：US15174338

申请日：2016-06-06

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Arkalgud R. Sitaram ,  Cyprian Emeka Uzoh

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L25/00 ,  H01L23/367 ,  H01L23/42

CPC classification number: H01L25/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31105 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5386 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.

公开(公告)号：US09691702B2

公开(公告)日：2017-06-27

申请号：US15200554

申请日：2016-07-01

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/04 ,  H01L23/52 ,  H01L21/44 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US09570385B2

公开(公告)日：2017-02-14

申请号：US14602984

申请日：2015-01-22

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K3/02 ,  H05K3/10 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/16 ,  H05K3/18

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

Abstract translation: 内插器电路（130）由可能牺牲的基板（210）形成，所述牺牲基板（210）从由导电涂层（130“）覆盖的多孔芯（130'）形成，所述导电涂层增加导电性。 核心由纳米颗粒油墨印刷。 然后形成支撑件（120S），例如 通过模制，以机械地稳定电路。 在形成电路或支撑件的同时，可以使用磁场来稳定电路。 还提供其他功能。

公开(公告)号：US20170040270A1

公开(公告)日：2017-02-09

申请号：US14819744

申请日：2015-08-06

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Bongsub Lee ,  Scott McGrath ,  Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Akash Agrawal

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/311

CPC classification number: H01L24/03 ,  H01L21/31144 ,  H01L21/486 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/03009 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/10126 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.

Abstract translation: 处理互连元件的方法可以包括提供具有前后相对表面和导电结构的衬底元件，覆盖前表面的第一电介质层和在第一介电层的第一表面处的多个导电触点，以及 第二电介质层覆盖在后表面上并且在第二介电层的第二表面处具有导电元件。 该方法还可以包括去除第二电介质层的一部分以减小该部分的厚度，并且提供具有第一厚度的第二介电层的凸起部分和具有第二厚度的下降部分。 第一厚度可以大于第二厚度。 导电元件的至少一部分可以凹陷到第二介电层的第一厚度的高度以下。

公开(公告)号：US20160315047A1

公开(公告)日：2016-10-27

申请号：US15200554

申请日：2016-07-01

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Abstract translation: 在具有穿过衬底（104）并且突出在衬底上方的导电通路（114）的微电子部件中，导电特征（120E.A，120E.B）设置在衬底上方，该衬底环绕导电通孔突起（114'） ）以形成电容器，电磁屏蔽以及可能的其他元件。 还提供了其它特征和实施例。

公开(公告)号：US09397038B1

公开(公告)日：2016-07-19

申请号：US14633746

申请日：2015-02-27

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L21/44 ,  H01L23/04 ,  H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Abstract translation: 在具有穿过衬底（104）并且突出在衬底上方的导电通路（114）的微电子部件中，导电特征（120E.A，120E.B）设置在衬底上方，该衬底环绕导电通孔突起（114'） ）以形成电容器，电磁屏蔽以及可能的其他元件。 还提供了其它特征和实施例。

公开(公告)号：US20160079169A1

公开(公告)日：2016-03-17

申请号：US14489358

申请日：2014-09-17

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Charles G. Woychik ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5328 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/83 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/014

Abstract: An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130) which is conductive and/or is coated with a conductive material (144). Such interconnects replace metal bond wires in some embodiments. Other features are also provided.

Abstract translation: 适于将集成电路组件彼此连接的互连（124）包括导电和/或涂覆有导电材料（144）的聚合物构件（130）。 在一些实施例中，这种互连替代金属接合线。 还提供其他功能。

公开(公告)号：US20150348940A1

公开(公告)日：2015-12-03

申请号：US14289483

申请日：2014-05-28

Applicant: Invensas Corporation

Inventor： Charles G. WOYCHIK ,  Arkalgud R. Sitaram ,  Andrew Cao ,  Bong-Sub Lee

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/48 ,  H01L23/373 ,  H01L23/367 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/29 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/481 ,  H01L24/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13193 ,  H01L2224/14155 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29388 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014

Abstract: A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.

Abstract translation: 形成半导体封装的方法包括在衬底的第一侧中形成一个或多个第一通孔并将第一微电子元件的第一侧附接到衬底的第一侧。 第一微电子元件电耦合到一个或多个第一通孔中的至少一个。 该方法还包括获得第二微电子元件，该第二微电子元件包括在第二微电子元件的第一侧中的一个或多个第二通孔，以及将该基板的第二侧附接到第二微电子元件的第一侧。 第二微电子元件电耦合到一个或多个第一通孔中的至少一个。 一个或多个连接元件中的每一个具有连接到第二微电子元件的第一侧的第一端，并且第二端延伸超过第一微电子元件的第二侧。