公开(公告)号：US20200271860A1

公开(公告)日：2020-08-27

申请号：US16285234

申请日：2019-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: G02B6/12 ,  G02B6/30 ,  G02B6/122 ,  G02B6/43

Abstract: A semiconductor package includes a photonic integrated circuit, an encapsulating material, and a redistribution structure. The photonic integrated circuit includes a coupling surface, a back surface opposite to the coupling surface and a plurality of optical couplers disposed on the coupling surface and configured to be coupled to a plurality of optical fibers. The encapsulating material encapsulates the photonic integrated circuit and revealing the plurality of optical couplers. The redistribution structure is disposed over the encapsulating material and the back surface of the photonic integrated circuit, wherein the redistribution structure is electrically connected to the photonic integrated circuit.

公开(公告)号：US10679915B2

公开(公告)日：2020-06-09

申请号：US16172836

申请日：2018-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Hsieh ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/02 ,  H01L23/31 ,  H01L25/18 ,  H01L21/56 ,  H01L23/532 ,  H01L23/00 ,  H01L21/82

Abstract: A package structure includes a plurality of first dies, a first encapsulant, and a first redistribution structure. The first encapsulant encapsulates the first dies. The first redistribution structure is disposed on the first dies and the first encapsulant. The first redistribution structure includes a dielectric layer covering a top surface and sidewalls of the first encapsulant.

公开(公告)号：US10672752B2

公开(公告)日：2020-06-02

申请号：US16158244

申请日：2018-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L25/00 ,  H01L25/10 ,  H01L21/50 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/60

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.

公开(公告)号：US10163875B2

公开(公告)日：2018-12-25

申请号：US15915534

申请日：2018-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Hui Cheng ,  Po-Hao Tsai ,  Jing-Cheng Lin ,  Yi-Hang Lin

IPC: H01L23/48 ,  H01L25/10 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48

Abstract: A method for forming a chip package structure is provided. The method includes forming a chip on an adhesive layer. The chip has a front surface and a back surface opposite to the front surface. The back surface is in direct contact with the adhesive layer. A first maximum length of the adhesive layer is less than a second maximum length of the chip. The method includes forming a molding compound layer surrounding the chip and the adhesive layer. A first bottom surface of the adhesive layer is substantially coplanar with a second bottom surface of the molding compound layer. The method includes forming a redistribution structure over the chip and the molding compound layer.

公开(公告)号：US20180315733A1

公开(公告)日：2018-11-01

申请号：US15499901

申请日：2017-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai ,  Chih-Chien Pan

IPC: H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/78 ,  H01L21/67

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/67207 ,  H01L21/78 ,  H01L24/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/02379 ,  H01L2224/10145 ,  H01L2224/13024 ,  H01L2224/14181 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/73259 ,  H01L2224/81007 ,  H01L2224/95001 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package, a manufacturing method for the semiconductor package and a printing module used thereof are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias, a polymeric cover film covering the molding compound and the die and polymeric dam structures disposed aside the connectors. The polymeric cover film and the polymeric dam structures are formed by printing.

公开(公告)号：US10115675B2

公开(公告)日：2018-10-30

申请号：US15235114

申请日：2016-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/60

Abstract: In accordance with some embodiments of the present disclosure, a packaged semiconductor device includes a first package structure, at least one outer conductive bump, a second package structure, a sealing material, and an electromagnetic interference (EMI) shielding layer. The first package structure has a first cut edge. The outer conductive bump is disposed on the first package structure and has a second cut edge. The second package structure is jointed onto the first package structure. The sealing material is disposed on the first package structure, surrounds the second package structure, and covers the outer conductive bump. The sealing material has a third cut edge. The EMI shielding layer contacts the first cut edge, the second cut edge and the third cut edge. The EMI shielding layer is electrically connected with the outer conductive bump.

公开(公告)号：US20240371725A1

公开(公告)日：2024-11-07

申请号：US18775879

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Hung-Yu Chen ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/04 ,  H01L23/31 ,  H01L23/40

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

公开(公告)号：US12057432B2

公开(公告)日：2024-08-06

申请号：US16933593

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Li-Hui Cheng ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/96 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/02205 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/1027 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

公开(公告)号：US20240071847A1

公开(公告)日：2024-02-29

申请号：US17822470

申请日：2022-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Liao ,  Ping-Yin Hsieh ,  Chih-Hao Chen ,  Pu Wang ,  Li-Hui Cheng ,  Ying-Ching Shih

IPC: H01L23/10 ,  H01L21/52 ,  H01L21/56 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538

CPC classification number: H01L23/10 ,  H01L21/52 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/562 ,  H01L24/32 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29172 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/83447 ,  H01L2224/83455

Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.

公开(公告)号：US11830821B2

公开(公告)日：2023-11-28

申请号：US17150300

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Semiconductor devices and methods of manufacture are provided, in which an adhesive is removed from a semiconductor die embedded within an encapsulant, and an interface material is utilized to remove heat from the semiconductor device. The removal of the adhesive leaves behind a recess adjacent to a sidewall of the semiconductor, and the recess is filled.