公开(公告)号：US07671466B2

公开(公告)日：2010-03-02

申请号：US11647832

申请日：2006-12-29

申请人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/34 ,  H05K7/20 ,  H01L21/00

CPC分类号： H01L23/473 ,  H01L21/563 ,  H01L23/3157 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253

摘要： A semiconductor package with a heat dissipating device and a fabrication method of the semiconductor package are provided. A chip is mounted on a substrate. The heat dissipating device is mounted on the chip, and includes an accommodating room, and a first opening and a second opening that communicate with the accommodating room. An encapsulant is formed between the heat dissipating device and the substrate to encapsulate the chip. A cutting process is performed to remove a non-electrical part of structure and expose the first and second openings from the encapsulant. A cooling fluid is received in the accommodating room to absorb and dissipate heat produced by the chip. The heat dissipating device covers the encapsulant and the chip to provide a maximum heat transfer area for the semiconductor package.

摘要翻译： 提供了具有散热装置的半导体封装和半导体封装的制造方法。 芯片安装在基板上。 散热装置安装在芯片上，并且包括容纳室，以及与容纳室连通的第一开口和第二开口。 在散热装置和衬底之间形成密封剂以封装芯片。 执行切割处理以去除结构的非电气部分，并使第一和第二开口与密封剂暴露。 冷却流体容纳在容纳室中以吸收和散发由芯片产生的热量。 散热装置覆盖密封剂和芯片，以为半导体封装提供最大的传热面积。

公开(公告)号：US07489044B2

公开(公告)日：2009-02-10

申请号：US11592046

申请日：2006-11-01

申请人： Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a semiconductor package and a fabrication method thereof. The method includes the steps of: providing a chip carrier module having a plurality of chip carriers, disposing a plurality of electrical connecting points on the chip carriers, performing chip mounting and molding on the chip carrier module to form an encapsulant encapsulating the semiconductor chip, exposing the electrical connecting points from the encapsulant; forming a patterned circuit layer on the encapsulant, electrically connecting the patterned circuit layer to the electrical connecting points, cutting and separating the chip carriers to form a plurality of semiconductor packages each having a circuit layer formed on the encapsulant such that the circuit layer provides extra electrical connecting points and thereby enhances electrical performance of electrical products. During a package stacking process, no package is limited by the design of another package below.

摘要翻译： 本发明提供半导体封装及其制造方法。 该方法包括以下步骤：提供具有多个芯片载体的芯片载体模块，在芯片载体上布置多个电连接点，在芯片载体模块上执行芯片安装和模制以形成封装半导体芯片的密封剂， 将电连接点暴露于密封剂; 在所述密封剂上形成图案化电路层，将所述图案化电路层电连接到所述电连接点，切割和分离所述芯片载体以形成多个半导体封装，每个半导体封装具有形成在所述密封剂上的电路层，使得所述电路层提供额外的 电连接点，从而提高电气产品的电气性能。 在包装堆垛过程中，没有包装受下面另一包装的设计限制。

公开(公告)号：US20070296079A1

公开(公告)日：2007-12-27

申请号：US11818225

申请日：2007-06-12

申请人： Chien-Ping Huang ,  Han-Ping Pu ,  Ho-Yi Tsai

发明人： Chien-Ping Huang ,  Han-Ping Pu ,  Ho-Yi Tsai

IPC分类号： H01L23/34 ,  H01L21/58

CPC分类号： H01L23/4334 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A heat sink package structure and a method for fabricating the same are disclosed. The method includes mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interface layer or a second heat dissipating element having the interface layer on the semiconductor chip and installing a first heat dissipating element having a heat dissipating portion and a supporting portion onto the chip carrier. The method further includes forming openings corresponding to the semiconductor chip in the heat dissipating portion, and forming an encapsulant for covering the semiconductor chip, the interface layer or the second heat dissipating element, and the first heat dissipating element. A height is reserved on top of the interface layer for the formation of the encapsulant for covering the interface layer. The method further includes cutting the encapsulant along edges of the interface layer, and removing the redundant encapsulant on the interface layer. Therefore, the drawbacks of the prior art of the burrs caused by a cutting tool for cutting the heat dissipating element and wearing of the cutting tool are overcome.

摘要翻译： 公开了一种散热器封装结构及其制造方法。 该方法包括将半导体芯片安装并电连接到芯片载体，在半导体芯片上形成具有界面层的界面层或第二散热元件，并将具有散热部分和支撑部分的第一散热元件安装到 芯片载体。 该方法还包括形成对应于散热部分中的半导体芯片的开口，以及形成用于覆盖半导体芯片，界面层或第二散热元件的密封剂和第一散热元件。 在接口层顶部保留一个高度，用于形成覆盖界面层的密封剂。 该方法还包括沿着界面层的边缘切割密封剂，以及去除界面层上的冗余密封剂。 因此，克服了用于切割散热元件的切削工具和切削工具的磨损引起的毛刺现有技术的缺陷。

公开(公告)号：US07247934B2

公开(公告)日：2007-07-24

申请号：US11026933

申请日：2004-12-29

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H05K1/141 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10689 ,  H01L2224/81 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.

摘要翻译： 提供一种多芯片半导体封装及其制造方法。 至少一个第一芯片通过焊料凸块安装在基板的上表面上并电连接到基板的上表面。 具有第二芯片和第一封装体的预制封装结构安装在基板的上表面上，其中预成型封装结构的外引线从第一封装体露出并电连接到基板的上表面。 第一封装体，外引线和衬底形成接收第一芯片的空间，并且在第一芯片和第一封装体之间存在间隙。 第二封装体形成在衬底的上表面上，以封装第一芯片，焊料凸块和预成型封装结构。 在基板的下表面上注入多个焊球。

公开(公告)号：US20060160348A1

公开(公告)日：2006-07-20

申请号：US11100140

申请日：2005-04-05

申请人： Han-Ping Pu ,  Chun-Chi Ke ,  Kuo-Jui Tai ,  Cheng-Hsu Hsiao

发明人： Han-Ping Pu ,  Chun-Chi Ke ,  Kuo-Jui Tai ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor element with under bump metallurgy (UBM) structures and a fabrication method thereof are proposed. When UBM structures are formed on signal pads and ground pads on a surface of the semiconductor element that is completely fabricated with a circuit layout, a metallic layer for defining the UBM structures is retained, wherein the UBM structures on the ground pads are electrically connected to the metallic layer, and the UBM structures on the signal pads are electrically insulated from the metallic layer. This allows the metallic layer for defining the UBM structures to directly serve as a grounding layer for the semiconductor element.

摘要翻译： 提出了具有凸块下冶金（UBM）结构的半导体元件及其制造方法。 当在完全由电路布局制造的半导体元件的表面上的信号焊盘和接地焊盘上形成UBM结构时，保留用于限定UBM结构的金属层，其中接地焊盘上的UBM结构电连接到 金属层和信号焊盘上的UBM结构与金属层电绝缘。 这允许用于限定UBM结构的金属层直接用作半导体元件的接地层。

公开(公告)号：US20060097402A1

公开(公告)日：2006-05-11

申请号：US11267707

申请日：2005-11-03

申请人： Han-Ping Pu ,  Chien-Ping Huang

发明人： Han-Ping Pu ,  Chien-Ping Huang

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L25/03 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2224/0401

摘要： A semiconductor device having a flip-chip package and a method for fabricating the same are provided. A flip-chip package after being tested to be functionally workable is mounted on a carrier and is electrically connected to the carrier by a plurality of first conductive elements, the flip-chip package having a first chip mounted on a substrate in a flip-chip manner. At least a second chip is mounted on the flip-chip package and is electrically connected to the carrier by a plurality of second conductive elements. An encapsulant is formed on the carrier for encapsulating the flip-chip package and the second chip. A plurality of solder balls are implanted on a bottom surface of the carrier, such that the first and second chips can be electrically connected to an external device via the solder balls. The above arrangement can effectively improve the yield of a fabricated product and reduce packaging costs.

摘要翻译： 提供了一种具有倒装芯片封装的半导体器件及其制造方法。 被测试在功能上可操作的倒装芯片封装安装在载体上并且通过多个第一导电元件与载体电连接，该倒装芯片封装具有安装在基板上的倒装芯片 方式。 至少第二芯片安装在倒装芯片封装上，并通过多个第二导电元件与载体电连接。 在载体上形成密封剂，用于封装倒装芯片封装和第二芯片。 在载体的底面上注入多个焊球，使得第一芯片和第二芯片可以经由焊球电连接到外部装置。 上述布置可以有效地提高制成品的产量并降低包装成本。

公开(公告)号：US20060017145A1

公开(公告)日：2006-01-26

申请号：US11212182

申请日：2005-08-26

申请人： Chang-Fu Lin ,  Han-Ping Pu ,  Cheng-Hsu Hsiao ,  Chien Huang

发明人： Chang-Fu Lin ,  Han-Ping Pu ,  Cheng-Hsu Hsiao ,  Chien Huang

IPC分类号： H01L23/06

CPC分类号： H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16315 ,  H01L2924/19105 ,  H01L2924/00014

摘要： A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.

摘要翻译： 提供了具有散热器的半导体封装，其中至少一个芯片安装在基板上并被散热器覆盖。 散热器在与基板接触的位置处形成有多个凹槽或孔，允许将粘合材料施加在散热器和基板之间并填充到用于将散热器附接到基板上的凹槽或孔中。 填充到槽或孔中的粘合剂材料提供了将散热器牢固地定位在基板上的锚固效果。 因此，不需要在基板上形成预定的孔，用于连接诸如螺栓的固定构件，并且散热器的结合不会影响迹线布线性以及诸如衬底上的焊球等输入/输出连接的布置 不会导致芯片的裂纹。

公开(公告)号：US20050200006A1

公开(公告)日：2005-09-15

申请号：US11126110

申请日：2005-05-09

申请人： Han-Ping Pu ,  Chieng Huang

发明人： Han-Ping Pu ,  Chieng Huang

IPC分类号： H01L21/60 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L23/34

CPC分类号： H01L23/3128 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/3862 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.

公开(公告)号：US06943439B2

公开(公告)日：2005-09-13

申请号：US10116204

申请日：2002-04-04

申请人： Chien-Ping Huang ,  Han-Ping Pu ,  Chih-Chin Liao

发明人： Chien-Ping Huang ,  Han-Ping Pu ,  Chih-Chin Liao

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/544 ,  H05K1/02 ,  H05K3/24 ,  H05K3/28 ,  H05K3/34 ,  H01L23/02 ,  H01L23/48 ,  H01L23/495 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/85 ,  H01L21/4846 ,  H01L22/34 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48 ,  H01L2224/8501 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K1/0269 ,  H05K3/242 ,  H05K3/28 ,  H05K3/3489 ,  H05K2201/09781 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A substrate and a fabrication method thereof are proposed, with at least a check point being formed on the substrate. Prior to wire bonding and/or molding processes, cleanness of the substrate (cleaned by plasma) is determined according to color variation of the check point, so as to allow only cleaned and contamination-free substrates to be subsequently formed with bonding wires and encapsulants thereon. Thereby, qualities of wire-bonded electrical connection and encapsulant adhesion for the substrate can be assured, which helps prevent the occurrence of delamination between the encapsulant and the substrate. Moreover, the check point formed on the substrate is made during general substrate fabrication by using current equipment and technique, and in a manner as not to interfere with trace routability on the substrate; thereby, costs and complexity of substrate fabrication would not undesirably increased.

摘要翻译： 提出了一种基板及其制造方法，至少在基板上形成检查点。 在引线接合和/或模制工艺之前，根据检查点的颜色变化确定基材的清洁度（通过等离子体清洁），以便仅使用清洁和无污染的基材随后用接合线和密封剂形成 上。 因此，可以确保线接合电连接的质量和用于衬底的密封剂附着性，这有助于防止密封剂和衬底之间的分层的发生。 此外，通过使用当前的设备和技术，在通常的基板制造中形成的检查点，并且以不干扰基板上的迹线布线性的方式进行; 因此，衬底制造的成本和复杂性将不会不期望地增加。

公开(公告)号：US20050040524A1

公开(公告)日：2005-02-24

申请号：US10909029

申请日：2004-07-30

申请人： Han-Ping Pu ,  Chang-Fu Lin ,  Chien-Ping Huang

发明人： Han-Ping Pu ,  Chang-Fu Lin ,  Chien-Ping Huang

IPC分类号： H01L23/498 ,  H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15311

摘要： A chip carrier for a semiconductor chip is provided. A plurality of solder pads for bump soldering are formed on a chip mounting surface of the chip carrier, to allow a flip chip to be mounted and electrically connected to the chip carrier. A solder mask layer is formed on the chip carrier, wherein a plurality of openings are provided in the solder mask layer to expose the solder pads, and an outwardly opening extended portion is formed respectively from the openings corresponding to the solder pads having a relatively narrower pitch therebetween, so as to prevent formation of voids during an underfill process for filing a gap between the flip chip and the chip carrier.

摘要翻译： 提供了一种用于半导体芯片的芯片载体。 在芯片载体的芯片安装表面上形成用于凸块焊接的多个焊盘，以允许倒装芯片安装并电连接到芯片载体。 在芯片载体上形成焊料掩模层，其中在焊料掩模层中设置多个开口以露出焊盘，并且从对应于具有相对较窄的焊盘的开口分别形成向外开口的延伸部分 间隔，以防止在底部填充过程中形成空隙，以便在倒装芯片和芯片载体之间填充间隙。