公开(公告)号：US08699233B2

公开(公告)日：2014-04-15

申请号：US12990785

申请日：2009-05-11

Applicant: Petteri Palm ,  Risto Tuominen ,  Antti Iihola

Inventor： Petteri Palm ,  Risto Tuominen ,  Antti Iihola

IPC: H05K1/16 ,  H05K1/18 ,  H05K3/30

CPC classification number: H05K1/09 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/351 ,  H05K1/182 ,  H05K1/188 ,  H05K3/305 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Manufacturing method and circuit module, which comprises an insulator layer (1) and, inside the insulator layer (1), at least one component (6), which comprises contact areas (7), the material of which contains a first metal. On the surface of the insulator layer (1) are conductors (22), which comprise at least a first layer (12) and a second layer (32), in such a way that at least the second layer (32) contains a second metal. The circuit module comprises contact elements between the contact areas (7) and the conductors (22) for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area (7), an intermediate layer (2), which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (ACONT 1), between the intermediate layer (2) and the contact area (7) is less that the surface area (APAD) of the contact area (7).

Abstract translation: 制造方法和电路模块包括绝缘体层（1）和绝缘体层（1）内部的至少一个部件（6），其包括接触区域（7），其材料包含第一金属。 在绝缘体层（1）的表面上是包括至少第一层（12）和第二层（32）的导体（22），至少第二层（32）包含第二层 金属。 电路模块包括接触区域（7）和用于形成电触点的导体（22）之间的接触元件。 接触元件在其接触区域（7）的材料的表面上包括含有第三金属的中间层（2），使得第一，第二和第三金属 是不同的金属，中间层（2）和接触区域（7）之间的接触表面积（ACONT 1）小于接触区域（7）的表面积（APAD）。

公开(公告)号：US20140097009A1

公开(公告)日：2014-04-10

申请号：US14038190

申请日：2013-09-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kentaro KANEKO ,  Kazuhiro KOBAYASHI

IPC: H05K1/02

CPC classification number: H05K1/0296 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/421 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0346 ,  H05K2203/0554 ,  H01L2924/00012

Abstract: A wiring substrate includes a first wiring layer, a first insulating layer, a second wiring layer, and a first wiring pattern. The second wiring layer includes a first metal foil that is thinner than the first wiring layer. A first via in the first insulating layer connects the first and second wiring layers. The first via is arranged to fill a first through hole and a first recess. The first through hole extends through the first insulating layer and has a first open end with a first opening diameter and a second open end with a smaller second opening diameter. The first recess is in communication with the first through hole. The first recess has a larger diameter than the second opening diameter. The first metal foil includes a first opening communicating with the first through hole and having a larger opening diameter larger than the first opening diameter.

Abstract translation: 布线基板包括第一布线层，第一绝缘层，第二布线层和第一布线图案。 第二布线层包括比第一布线层薄的第一金属箔。 第一绝缘层中的第一通孔连接第一和第二布线层。 第一通孔布置成填充第一通孔和第一凹槽。 第一通孔延伸穿过第一绝缘层，并且具有第一开口直径的第一开口端和具有较小的第二开口直径的第二开口端。 第一凹槽与第一通孔连通。 第一凹部具有比第二开口直径更大的直径。 第一金属箔包括与第一通孔连通并且具有比第一开口直径大的开口直径的第一开口。

公开(公告)号：US20140083757A1

公开(公告)日：2014-03-27

申请号：US14035957

申请日：2013-09-25

Applicant: ZHEN DING TECHNOLOGY CO., LTD.

Inventor： WEN-HUNG HU

IPC: H05K1/02 ,  H05K3/42

CPC classification number: H05K1/0298 ,  H05K1/115 ,  H05K3/421 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49165

Abstract: A printed circuit board includes a first, second, and third dielectric layers, and a first, second, and third trace layers. The first trace layer and the second trace layer are formed on opposite surfaces of the first dielectric layer. The second dielectric layer is formed on the second trace layer, a first blind hole is defined in the first surface and terminated at a position in the first dielectric layer, a first conductive via is formed in the first blind hole. A second blind hole is formed in the second dielectric layer and the first dielectric layer. A second conductive via is formed in the second blind hole. The third trace layer is electrically connected with the second conductive via. The first trace layer is electrically connected with the second trace layer through the first conductive via and the second conductive via.

Abstract translation: 印刷电路板包括第一，第二和第三电介质层，以及第一，第二和第三迹线层。 第一迹线层和第二迹线层形成在第一介电层的相对表面上。 第二电介质层形成在第二迹线层上，第一盲孔被限定在第一表面中并且终止于第一电介质层中的位置，第一导电通孔形成在第一盲孔中。 在第二电介质层和第一电介质层中形成第二盲孔。 第二导电通孔形成在第二盲孔中。 第三迹线层与第二导电通孔电连接。 第一迹线层通过第一导电通孔和第二导电通孔与第二迹线层电连接。

公开(公告)号：US08674781B2

公开(公告)日：2014-03-18

申请号：US13621117

申请日：2012-09-15

Applicant: Heung-Kyu Kim

Inventor： Heung-Kyu Kim

IPC: H01P3/08

CPC classification number: H01P3/081 ,  H01P11/003 ,  H05K1/0221 ,  H05K3/205 ,  H05K2201/0376 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09827

Abstract: A printed circuit board having a micro strip line, a printed circuit board having a strip line and a method of manufacturing thereof are disclosed. The printed circuit board having a micro strip line in accordance with an embodiment of the present invention includes a first insulation layer, a signal line buried in one surface of the first insulation layer, a plurality of conductors penetrating through the first insulation layer and being disposed on both sides of the signal line in parallel with the signal line, and a ground layer formed to be electrically connected to the conductor on the other surface of the first insulation layer.

Abstract translation: 公开了一种具有微带线的印刷电路板，具有带状线的印刷电路板及其制造方法。 根据本发明实施例的具有微带线的印刷电路板包括第一绝缘层，埋在第一绝缘层的一个表面中的信号线，穿过第一绝缘层并被布置的多个导体 在与信号线并联的信号线的两侧，以及形成为与第一绝缘层的另一个表面上的导体电连接的接地层。

公开(公告)号：US08593823B2

公开(公告)日：2013-11-26

申请号：US12588728

申请日：2009-10-26

Applicant: Tetsuya Ohsawa ,  Hayato Abe ,  Yoshinari Yoshida

Inventor： Tetsuya Ohsawa ,  Hayato Abe ,  Yoshinari Yoshida

IPC: H05K7/00

CPC classification number: G11B5/486 ,  G11B5/4853 ,  H05K1/056 ,  H05K1/181 ,  H05K3/06 ,  H05K3/445 ,  H05K2201/0394 ,  H05K2201/09081 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10545 ,  H05K2201/10727 ,  H05K2203/0323 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49167

Abstract: A suspension board with circuit includes a conductive pattern. The conductive pattern includes a first terminal provided on the front face of the suspension board with circuit and electrically connected with a magnetic head; and a second terminal provided on the back face of the suspension board with circuit and electrically connected with an electronic device.

Abstract translation: 具有电路的悬挂板包括导电图案。 导电图案包括设置在具有电路的悬挂板的前表面上并与磁头电连接的第一端子; 以及设置在具有电路的悬挂板的背面上并与电子设备电连接的第二端子。

公开(公告)号：US08586476B2

公开(公告)日：2013-11-19

申请号：US12874397

申请日：2010-09-02

Applicant: Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

Inventor： Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

IPC: H01L21/44

CPC classification number: H01L21/768 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/49165

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract translation: 电路基板使用后馈电顶部电源连接来提供改进的布线灵活性和较低的电源电压降/功率损耗。 在基板的外边缘附近使用电镀通孔，以提供与作为电源平面的管芯相邻的基板的顶部金属层的电源连接。 引脚插入通过电镀通孔以进一步降低电源路径的电阻。 引脚的底端可以延伸越过基板的底部以提供用于电源连接的可焊接互连，或者引脚的底端可以被焊接到基板的底部金属层上的“点动”电路图案，其连接 引脚连接到包括基板的集成电路封装的一个或多个电源端子。

公开(公告)号：US20130249112A1

公开(公告)日：2013-09-26

申请号：US13897202

申请日：2013-05-17

Applicant: Todd B. Myers ,  Nicolas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

Inventor： Todd B. Myers ,  Nicolas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US08497434B2

公开(公告)日：2013-07-30

申请号：US12651191

申请日：2009-12-31

Applicant: Jae-Seok Lee

Inventor： Jae-Seok Lee

IPC: H05K1/11

CPC classification number: H05K3/10 ,  H05K3/0097 ,  H05K3/061 ,  H05K3/205 ,  H05K3/22 ,  H05K3/28 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4658 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/054 ,  H05K2203/0571 ,  H05K2203/0574

Abstract: A printed circuit board and a manufacturing method of the same are disclosed. The method includes: preparing a carrier including a primer resin layer formed thereon; forming a circuit pattern on the primer resin layer; stacking the carrier onto an insulating layer such that the circuit pattern is buried in the insulating layer; removing the carrier; forming a via hole in the insulating layer on which the primer resin layer is stacked; and forming a conductive via in the via hole. The conductive via is formed by forming a plating layer in the via hole and on the primer resin layer and removing a portion of the plating layer formed over the primer resin layer.

Abstract translation: 公开了一种印刷电路板及其制造方法。 该方法包括：制备其上形成有底漆树脂层的载体; 在底漆树脂层上形成电路图案; 将载体堆叠在绝缘层上，使得电路图案埋在绝缘层中; 移除载体; 在其上层叠有底漆树脂层的绝缘层中形成通孔; 以及在所述通孔中形成导电通孔。 导电孔通过在通孔中和底漆树脂层上形成镀层而除去在底漆树脂层上形成的镀层的一部分而形成。

公开(公告)号：US08487446B2

公开(公告)日：2013-07-16

申请号：US13095317

申请日：2011-04-27

Applicant: Todd B Myers ,  Nicolas R Watts ,  Eric C Palmer ,  Jui Min Lim

Inventor： Todd B Myers ,  Nicolas R Watts ,  Eric C Palmer ,  Jui Min Lim

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US08471153B2

公开(公告)日：2013-06-25

申请号：US12186604

申请日：2008-08-06

Applicant: Hironori Tanaka ,  Keisuke Shimizu

Inventor： Hironori Tanaka ,  Keisuke Shimizu

IPC: H05K1/16 ,  H05K1/18

CPC classification number: H05K1/162 ,  H05K1/09 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/4913

Abstract: A multilayer printed wiring board includes a core substrate, a resin insulation layer laminated on the core substrate and a capacitor section coupled to the resin insulating layer. The capacitor section includes a first electrode including a first metal and configured to be charged by a negative charge, and a second electrode including a second metal and opposing the first electrode, the second electrode configured to be charged by a positive charge. A dielectric layer is interposed between the first electrode and second electrode, and an ionization tendency of the first metal is larger than and ionization tendency of the second metal.

Abstract translation: 多层印刷线路板包括芯基板，层叠在芯基板上的树脂绝缘层和耦合到树脂绝缘层的电容器部分。 电容器部分包括第一电极，其包括第一金属并被构造为通过负电荷充电;以及第二电极，包括第二金属并与第一电极相对，第二电极被配置为通过正电荷充电。 电介质层插入在第一电极和第二电极之间，第一金属的电离倾向大于第二金属的离子化倾向。